Data Sheet

4.4.3 Active Serial Configuration
1. After all steps in the previous section are completed, press push button S1
C10_NCONFIG or power cycle the board.
2. Yellow LED D5 will turn ON. This indicates that the FPGA is configured with the
image in flash under Active Serial Mode.
4.5 Status Elements
Table 8. LEDs
Board Reference Schematic Signal Name Color Description
D4
PWR_GD_LED
Blue Power Good LED (Detects
VCC_3.3V and VCC_1.2V)
ON: Detected Power is good
OFF: Detected Power is bad
D5
SYS_CONF_DONE
Yellow Configuration Done Status
Indicator
ON: FPGA configured
successfully
OFF: FPGA not configured
D10
ENET_LED0
Green Ethernet link status indicator
ON: Link-up
OFF: Link-down
Blink: Link-up with traffic
D11
ENET_LED1
Green Ethernet link speed indicator
ON: 100 Mbps
OFF: 10/1000 Mbps or Link-
down
D12
ENET_LED2
Green Ethernet link speed indicator
ON: 1000 Mbps
OFF: 10/100 Mbps or Link-
down
4.6 Setup Elements
Table 9. DIP Switches
Board Reference Schematic Signal Name Description
SW1.4
VTAP_BYPASSn
Pull low to disable Virtual JTAG TAP in
device chain
Table 10. Push Buttons
Board Reference Schematic Signal Name Description
S1
C10_nCONFIG
Press this push button to reconfigure
Intel Cyclone 10 LP FPGA device
S2
C10_RESETn
Press to do device-wide reset, connect
to Intel Cyclone 10 LP FPGA DEV_CLRn
4 Evaluation Board Components
UG-20082 | 2018.02.05
Intel
®
Cyclone
®
10 LP FPGA Evaluation Kit User Guide
21
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