Data Sheet

Feature Description
PLLs • Analog-based
• Low jitter
• High precision clock synthesis
• Clock delay compensation
• Zero delay buffering
• Multiple output taps
General-purpose I/Os (GPIOs) • Multiple I/O standards support
• On-chip termination (OCT)
• Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS
transmitter
External memory interface (EMIF) Supports up to 600 Mbps external memory interfaces:
• DDR3, DDR3L, DDR2, LPDDR2
• SRAM (Hardware support only)
Note: For 600 Mbps performance, –6 device speed grade is required.
Performance varies according to device grade (commercial, industrial, or
automotive) and device speed grade (–6 or –7). Refer to the MAX 10
Device Data Sheet or External Memory Interface Spec Estimator for more
details.
Configuration • Internal configuration
• JTAG
• Advanced Encryption Standard (AES) 128-bit encryption and compression
options
• Flash memory data retention of 20 years at 85 °C
Flexible power supply schemes • Single- and dual-supply device options
• Dynamically controlled input buffer power down
• Sleep mode for dynamic power reduction
Related Links
MAX 10 FPGA Device Overview
4.4 FPGA Configuration
The Intel Cyclone 10 LP FPGA Evaluation Board supports two configuration methods:
• Configuration by downloading a .sof file to the FPGA. Any power cycling of the
FPGA or reconfiguration will power up the FPGA to a blank state.
• Programming of the board EPCQ or EPCQ-A flash with a .jic file. Any power cycling
of the FPGA or reconfiguration will lead to reconfigure from flash with AS mode.
You can use two different Intel FPGA Download Cable hardware components to
program the .sof or .jic files:
• Embedded Intel FPGA Download Cable II type-B mini-USB connector (J17)
• JTAG header (J2). Use an external Intel FPGA Download Cable, Intel FPGA
Download Cable II or Ethernet Blaster download cable. The external download
cable connects to the board through the JTAG header (J2).
4.4.1 Using the Quartus Prime Programmer
You can use the Intel Quartus Prime Programmer to configure the FPGA with a .sof.
4 Evaluation Board Components
UG-20082 | 2018.02.05
Intel
®
Cyclone
®
10 LP FPGA Evaluation Kit User Guide
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