Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide Subscribe Send Feedback Downloaded from Arrow.com. UG-20082 | 2018.02.
Contents Contents 1 Overview......................................................................................................................... 4 1.1 Evaluation Kit Description........................................................................................ 4 1.1.1 Evaluation Board Description........................................................................ 4 1.1.2 Evaluation Kit Collateral...............................................................................5 1.1.
Contents 6.2 6.3 6.4 6.5 6.6 6.7 The The The The The The System Info Tab............................................................................................. 42 GPIO Tab....................................................................................................... 43 Flash Tab....................................................................................................... 44 HyperRAM Tab................................................................................................
UG-20082 | 2018.02.05 1 Overview The Intel® Cyclone® 10 LP Evaluation Kit provides an easy-to-use platform for evaluating the performance and features of the Intel Cyclone 10 LP FPGA device. 1.
1 Overview UG-20082 | 2018.02.
1 Overview UG-20082 | 2018.02.05 AC/DC Adapter Power Caution: Use 5 V adapter for DC Jack J12 only. Components on the board can get damaged by power supplies with greater voltage. 1.2 Recommended Operating Conditions • Recommended ambient operating temperature range: 0C to 45C • Maximum VCCINT current: 0.6 A • Maximum board power consumption: 3 A @ 5 V when powered by AC/DC adapter 1.3 Handling the Board When handling the board, it is important to observe static discharge precautions.
1 Overview UG-20082 | 2018.02.05 Figure 1. Intel Cyclone 10 LP Evaluation Board Part Number Label The following table shows the board revision and flash memory type corresponding to the part number. Table 1. Intel Cyclone 10 LP Evaluation Board Revision and Flash Type Part Number Board Revision Flash Memory Type 6XX-44504R-0C or earlier A1 EPCQ64 6XX-44504R-0D or later A2 EPCQ128A Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide 7 Downloaded from Arrow.com.
UG-20082 | 2018.02.05 2 Getting Started 2.1 Installing Quartus Prime Software To download the Intel Quartus Prime Standard Edition software, go to the Quartus Prime Standard Edition page in the Intel Download Center. About Intel Quartus Prime Software The Intel Quartus Prime design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs.
2 Getting Started UG-20082 | 2018.02.05 Figure 2. Evaluation Kit Directory Structure board_design_files demos documents examples factory_recovery The table below lists the file directory names and a description of their contents Table 2. Directory Structure File Directory Name Description of Directory Contents board_design_files Contains schematics, layout, assembly and bill of material board design files.
UG-20082 | 2018.02.05 3 Evaluation Board Setup The instructions in this chapter explain how to set up the Intel Cyclone 10 LP FPGA Evaluation Board. 3.1 Powering Up the Evaluation Board There are two power supply options provided for the Intel Cyclone 10 LP FPGA Evaluation Board. The first is USB powered and the second is external AC/DC adapter powered. These two options can be used for different applications.
3 Evaluation Board Setup UG-20082 | 2018.02.05 Table 3. DIP Switch Settings Switch Board Label Default Position Function SW1.4 BYPASS OPEN/OFF/1 Virtual JTAG TAP Enable SW1.3 DIP0 OPEN/OFF/1 Switch 0 SW1.2 DIP1 OPEN/OFF/1 Switch 1 SW1.1 DIP2 OPEN/OFF/1 Switch 2 3.3 Recovering Factory Default Settings To restore the evaluation board to factory default settings, perform the following steps. 1.
3 Evaluation Board Setup UG-20082 | 2018.02.05 Figure 3. Board Test System GUI with Restore Menu 4. Fill in the text boxes with your board details, as shown in the example below, and click Restore. The restore process takes several minutes. Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide 12 Downloaded from Arrow.com.
3 Evaluation Board Setup UG-20082 | 2018.02.05 Figure 4. Restoring Factory Defaults on the Intel Cyclone 10 LP LP FPGA Evaluation Board Related Links Intel FPGA Download Center Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide 13 Downloaded from Arrow.com.
UG-20082 | 2018.02.05 4 Evaluation Board Components This chapter introduces all important components on the evaluation board. 4.1 Board Overview This topic provides a high-level list of major components on the Intel Cyclone 10 LP FPGA evaluation board. Figure 5. Intel Cyclone 10 LP FPGA Evaluation Board Block Diagram Arduino Analog Arduino Header PMOD Header Arduino Digital Mini-USB 2.
4 Evaluation Board Components UG-20082 | 2018.02.05 Board Reference Type Description U26, U27 Power Regulator Enpirion EP5358HUI, 600 mA PowerSoC DC-DC step-down converters with integrated inductor.
4 Evaluation Board Components UG-20082 | 2018.02.05 Board Reference Type SW1.1 - SW1.3 Description User DIP Switches 3-bit user DIP switches Memory Devices U13 HyperRAM Memory 128 Mb x8 HyperRAM with 1.
4 Evaluation Board Components UG-20082 | 2018.02.05 Intel Cyclone 10 LP FPGA Feature Summary Intel Cyclone 10 LP FPGA devices provide a high-density sea of programmable gates, on-board resources, and general purpose I/Os. These resources satisfy the requirements of I/O expansion and chip-to-chip interfacing. The Intel Cyclone 10 LP FPGA architecture suits smart and connected end applications across many market segments: Table 6.
4 Evaluation Board Components UG-20082 | 2018.02.05 4.3 MAX 10 System Controller Overview The highlights of the Intel MAX 10 devices include: • Internally stored dual configuration flash • User flash memory • Instant on support • Integrated analog-to-digital converter (ADC) • Single-chip Nios II soft core processor support Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications. Table 7.
4 Evaluation Board Components UG-20082 | 2018.02.
4 Evaluation Board Components UG-20082 | 2018.02.05 Before configuring the FPGA • Ensure that the Intel Quartus Prime Programmer and the Intel FPGA Download Cable driver are installed on the host computer. • The USB cable is connected to the board. • Power to the board is on, and no other applications that use the JTAG chain are running. To configure the Intel Cyclone 10 LP FPGA 1. Start the Intel Quartus Prime Programmer. 2. Click Add File and select the path to the desired .sof. 3.
4 Evaluation Board Components UG-20082 | 2018.02.05 4.4.3 Active Serial Configuration 1. After all steps in the previous section are completed, press push button S1 C10_NCONFIG or power cycle the board. 2. Yellow LED D5 will turn ON. This indicates that the FPGA is configured with the image in flash under Active Serial Mode. 4.5 Status Elements Table 8. LEDs Board Reference Schematic Signal Name Color Description D4 PWR_GD_LED Blue Power Good LED (Detects VCC_3.3V and VCC_1.
4 Evaluation Board Components UG-20082 | 2018.02.05 4.7 General User Input/Output Table 11. DIP Switches Board Reference Schematic Signal Name FPGA Signal Name Description SW1.3 USER_DIP0 U1.M16 User-defined Switch0 SW1.2 USER_DIP1 U1.A8 User-defined Switch1 SW1.1 USER_DIP2 U1.A9 User-defined Switch2 Table 12. Push Buttons Board Reference Schematic Signal Name FPGA Signal Name Description S3 USER_PB0 U1.E15 User-defined PB0 S4 USER_PB1 U1.
4 Evaluation Board Components UG-20082 | 2018.02.05 Figure 6. Intel Cyclone 10 LP FPGA Clock Tree USB_CLK Cypress CY7C68013A USB Controller 24 MHz Crystal MAX 10 On-Board Intel® FPGA Download Cable II M10_CLK50M 6 7 1 8 C10_CLK50M 2 5 Cyclone 10 LP Si50 50 MHz Oscillator 3 Default LVCMOS 125 MHz Si5351 Default LVCMOS 50 MHz 25 MHz Crystal LVCMOS Adjustable 4 ENET_CLK_125M HBUS_CLK_50M C10_CLK_ADJ 4.
4 Evaluation Board Components UG-20082 | 2018.02.05 Schematic Signal Name Schematic Shared Bus Signal Name FPGA Pin Number I/O Standard Direction @ FPGA Description ENET_RG_TXD3 C10_RG_TXD3 A2 3.3 V Out RGMII TX data 3 ENET_RG_TXCTL C10_RG_TXCTL D6 3.3 V Out RGMII TX control ENET_RG_RXCLK RG_RXCLK B8 3.3 V In RGMII RX Clock ENET_RG_RXD0 RG_RXD0 A7 3.3 V In RGMII RX data 0 ENET_RG_RXD1 RG_RXD1 B7 3.3 V In RGMII RX data 1 ENET_RG_RXD2 RG_RXD2 A6 3.
4 Evaluation Board Components UG-20082 | 2018.02.05 4.9.2 2x20 GPIO Expansion Header The Intel Cyclone 10 LP FPGA evaluation board provides one 40-pin expansion GPIO header with up to 36 GPIO signals. This 2x20 GPIO Header is compatible with some Terasic 2x20 GPIO cards. There are also +5 V (VCC_5V_GPIO) and +3.3 V (VCC_3.3V) and two GND pins on 2x20 GPIO expansion header. All GPIO signals GPIO[0:35] are 3.3 V single-ended LVCMOS/LVTTL signals who are connected to Intel Cyclone 10 LP FPGA directly.
4 Evaluation Board Components UG-20082 | 2018.02.05 Board Reference Schematic Signal FPGA Pin Number Name J10.27 GPIO24 N5 3.3 V IO GPIO Signal 24 J10.28 GPIO25 N6 3.3 V IO GPIO Signal 25 J10.29 VCC_3.3V --- --- --- VCC_3.3V J10.30 GND --- --- --- Ground J10.31 GPIO26 R4 3.3 V IO GPIO Signal 26 J10.32 GPIO27 T4 3.3 V IO GPIO Signal 27 J10.33 GPIO28 N3 3.3 V IO GPIO Signal 28 J10.34 GPIO29 P3 3.3 V IO GPIO Signal 29 J10.35 GPIO30 R3 3.
4 Evaluation Board Components UG-20082 | 2018.02.05 The maximum power output capability is shown in the table below. When using 2x20 GPIO Header, USB may not provide sufficient power. Hence, use an external adapter connector (J12) to power up the board. Table 16. 2X20 GPIO Header Power Output Capability PowerRail Output Pin Location Max Current Note VCC_5V_GPIO J10.11 0.5 A VCC_5V output capability to card (depends on the power adapter capability) VCC_3.3V J10.29 0.5 A VCC_3.
4 Evaluation Board Components UG-20082 | 2018.02.05 Table 17. Arduino Connector Board Reference Schematic Signal FPGA Pin Number Name I/O Standard Direction @ FPGA Description Header 1 (PWR) J4.1 NC --- J4.2 IOREF --- --- --- Connected to VCC_3.3V J4.3 ARDUINO_RSTn L3 3.3 V In Arduino Reset Input J4.4 VCC_3.3V --- J4.5 VCC_5V_AR1 J4.6 GND J4.7 GND J4.8 NC Header 2 (Analog) J6.1 ARDUINO_ANA0 --- Analog In Arduino Analog Channel 0 J6.
4 Evaluation Board Components UG-20082 | 2018.02.05 Board Reference Schematic Signal FPGA Pin Number Name I/O Standard Direction @ FPGA Description Header 4 (Digital) J7.1 ARDUINO_IO0 B1 3.3 V IO Arduino Digital Bit 0 J7.2 ARDUINO_IO1 C2 3.3 V IO Arduino Digital Bit 1 J7.3 ARDUINO_IO2 F3 3.3 V IO Arduino Digital Bit 2 J7.4 ARDUINO_IO3 D1 3.3 V IO Arduino Digital Bit 3 J7.5 ARDUINO_IO4 G2 3.3 V IO Arduino Digital Bit 4 J7.6 ARDUINO_IO5 G1 3.
4 Evaluation Board Components UG-20082 | 2018.02.05 Table 18. Arduino Channel Connections Arduino Connector ADC Channel MAX 10 ADC Name MAX10 Pin ARDUINO_ANA0 (J6.1) ADC1 Channel5 ADC1IN5 U3.C1 ARDUINO_ANA1 (J6.2) ADC1 Channel0 (Dedicated Channel) ANAIN1 U3.D2 ARDUINO_ANA2 (J6.3) ADC1 Channel1 ADC1IN1 U3.D1 ARDUINO_ANA3 (J6.4) ADC1 Channel8 ADC1IN8 U3.E1 ARDUINO_ANA4 (J6.5) ADC1 Channel7 ADC1IN7 U3.F1 ARDUINO_ANA5 (J6.6) ADC1 Channel4 ADC1IN4 U3.
4 Evaluation Board Components UG-20082 | 2018.02.05 1. Read value of 0x30 register address is 0xB9 and read value of 0x31 register address is 0x3, then the ADC output value is 0x3B9, or in decimal, 953. Hence, ADC_Output_Value=953 2. MAX 10 internal reference voltage is used so VREF = 3.3 V 3. Divider resistor values are R217 = 316 ohm and R216 = 316 ohm, so R_Divider = R217/R216 + 1 = 2 4. Calculated the analog signal voltage on ARDUINO_ANA0 (J6.1) is Voltage @ ARDUINO_ANA0 = (953/4096) * 3.
4 Evaluation Board Components UG-20082 | 2018.02.05 When using Arduino connector, USB may not provide sufficient power so we suggest you use external adapter connector (J12) to power up the board. Arduino UNO R3 did not specify limitation of output current capability. The following table shows the maximum output current for the Intel Cyclone 10 LP FPGA Evaluation Board. Table 20. Arduino Power Output Capability Power Rail Output Pin Location Maximum Current Note VCC_5V_AR1 VCC_5V_AR2 J4.5 J18.2 0.
4 Evaluation Board Components UG-20082 | 2018.02.05 Table 22. Pmod Header Power Output Capability Power Rail Output Pin Location J8.6, J8.12 VCC_3.3 V Maximum Current 0.25A Note VCC_3.3 V output capability to Pmod module 4.10 Memory 4.10.1 HyperRAM HyperRAM is a portfolio of high-speed, low-pin-count memory product that uses the HyperBus interface technology. The Intel Cyclone 10 LP FPGA Evaluation Board supports HyperRAM with HyperBus Controller (HBMC) IP provided by Synaptic Labs.
4 Evaluation Board Components UG-20082 | 2018.02.05 Schematic Signal Name FPGA Pin Number I/O Standard Direction @ FPGA Description HBUS_CS1n N12 1.8 V OUT Chip Select for Hyper FLASH (Reserved Only) HBUS_RSTOn T15 1.8 V IN Reset Output from slave to master (Reserved Only) HBUS_INTn P11 1.8 V IN Interrupt Output from slave to master (Reserved Only) Note: The Synaptic Labs HyperBus® Memory Controller IP (HBMC) for Intel FPGA is available in a Basic Edition (OpenCore) and a Full Edition.
4 Evaluation Board Components UG-20082 | 2018.02.05 Table 25. Flash Memory Map Block Description Size (KB) Address Comments Board Test System Scratch 512 0x0073.0000 - 0x007A.FFFF BTS System Testing Board Information 64 0x0072.0000 - 0x0072.FFFF Board Information Ethernet Option Bits 64 0x0071.0000 - 0x0071.FFFF MAC Address Information User Design Reset Vector 64 0x0070.0000 - 0x0070.FFFF Nios II Reset Vector Information Factory Software (ELF) 4096 0x0030.0000 - 0x006F.
4 Evaluation Board Components UG-20082 | 2018.02.05 Table 27. USB Ports Port Description P1 • • • USB Standard A Plug. Connects to USB host Used for both USB signals and USB VBUS 5 V P2 • • Complementary USB Standard A plug for additional USB VBUS 5 V power. No signal connection. P3 • • USB Mini-B Plug Connected to USB Port J17 When P1 and P2 are plugged into USB Host ports at the same time, it can supply up to 1A current to the Intel Cyclone 10 LP FPGA Evaluation Board. Figure 11.
4 Evaluation Board Components UG-20082 | 2018.02.05 Related Links • Powering Up the Evaluation Board on page 10 • Evaluation Kit Description on page 4 4.11.2 Power Tree Figure 12. Intel Cyclone 10 LP FPGA Evaluation Board Power Tree VCC_5V USB_5V (1 A) 5V_DCIN (>1 A) VCC_5V EN5339QI (U23) 3 A Maximum VCC_3.3V EN5329QI (U25) 2 A Maximum VCC_1.2V EN5358HUI (U26) 0.6 A Maximum VCC_1.8V EN5358HUI (U27) 0.6 A Maximum VCC_3.3V C10_VCCIO_3.3V C10_VCCINT C10_VCCD_PLL C10_VCCIO_1.
4 Evaluation Board Components UG-20082 | 2018.02.05 Figure 13. Current Measurement Current Sense Analog Channels Current Sense Amplifier MAX 10 10M08 U169 Logic Analog 3 Channels ADC Analog Arduino Analog 6 Channels Arduino Analog Channels Data UBII Avalon-MM ADC I2C Slave ADC I2C Graphical User Interface ADC I2C Master Cyclone 10 LP Other Intel Cyclone 10 LP FPGA power rails support manual measurement by measure voltage drop across sensing resistors with a multi-meter.
UG-20082 | 2018.02.05 5 Simple Socket Server The Intel Cyclone 10 LP FPGA Evaluation Board ships with the Simple Socket Server design example stored in the factory portion of the flash memory. The design consists of a Nios II embedded processor and an Ethernet MAC. Note: The Intel Cyclone 10 LP Evaluation Board Rev A1 hardware design does not include Ethernet MAC support. If you have a Rev A1 board, download and install the Rev A2 design.
5 Simple Socket Server UG-20082 | 2018.02.05 nios2-terminal.exe When the IP address is assigned, it is displayed as shown in the following figure. Figure 14. IP Address in Nios II Command Shell After configuring with the Simple Socket Server design example, you can see the four LEDs lighting at the same time. You can access the telnet server from the Nios II command shell as shown in the following figure. Figure 15.
UG-20082 | 2018.02.05 6 Board Test System The evaluation kit collateral includes an application called the Board Test System (BTS). The BTS provides an easy-to-use interface to alter the functional settings and observe the results. You can use the BTS to test board components, modify functional parameters, observe performance and measure power usage. While using the BTS, you can reconfigure the FPGA several times with test designs specific to the functionality you are testing. Figure 16.
6 Board Test System UG-20082 | 2018.02.05 The BTS communicates over the JTAG bus to a test design running in the FPGA. The BTS and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the Signal Tap Embedded Logic Analyzer. As the Intel Quartus Prime uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time-out. Note: Close other applications before attempting to reconfigure the FPGA using the Intel Quartus Prime Programmer. 6.
6 Board Test System UG-20082 | 2018.02.05 Figure 18. The System Info Tab Table 28. The System Info Tab Controls Controls Description Board Information The board information is updated once the GPIO design is configured. Otherwise, this control displays the default static information about your board. Board Name Indicates the official name of the board, given by the Board Test System. Board P/N Indicates the part number of the board. Serial Number Indicates the serial number of the board.
6 Board Test System UG-20082 | 2018.02.05 Figure 19. The GPIO Tab Table 29. The GPIO Tab Controls Control Description User LEDs Displays the current state of the user LEDs for the FPGA. To toggle the board LEDs, click the 0 to 3 buttons to toggle red or green LEDs, or click the All button. User DIP Switch Displays the current positions of the switches in the user DIP switch banks. Change the switches on the board to see the graphical display change accordingly.
6 Board Test System UG-20082 | 2018.02.05 Figure 20. The Flash Tab Control Description Read Reads the flash memory on your board. To see the flash memory contents, type a starting address in the text box and click Read. Values starting at the specified address appear in the table. Write Writes the flash memory on your board. To update the flash memory contents, change values in the table and click Write.
6 Board Test System UG-20082 | 2018.02.05 Figure 21. The HyperRAM Tab Table 30. The HyperRAM Tab Controls Control Description Speed (MByte/s) • Errors These controls display data errors detected during analysis and allow you to insert errors. • Detected—Displays the number of data errors detected in the hardware. • Inserted—Displays the number of errors inserted into the transaction stream. • Insert—Inserts a one-word error into the transaction stream each time you click the button.
6 Board Test System UG-20082 | 2018.02.05 Control Description Address Range (Bytes) Determines the number of addresses to use in each iteration of reads and writes. Test Times This item displays test times since you last clicked Start. Control • • • Burst Length—Allows you to change the burst length of the design. Supported burst lengths are 2, 4, 8, 16, 32, 64, and 128. Start—Start HyperRAM testing Stop—Stop HyperRAM testing 6.
6 Board Test System UG-20082 | 2018.02.05 This window displays Intel Cyclone 10 LP current monitors. Current shows the current value of each power rail: • 3.3 V VCCIO • 2.5 V VCCA • 1.2 V VCCINT Voltage shows the typical voltage value of each power rail. It is not read from ADC. Update Speed allows you to select how often the display updates the values: • Slow—every 2 seconds • Medium—every 500 ms • Fast (default)—every 100 ms 6.
6 Board Test System UG-20082 | 2018.02.05 Table 31. The Si5351 Tab Controls Control Description Fvco_A/Fvco_B Displays the generating signal value of the voltage-controlled oscillator. Frequency (KHz) Allows you to specify the frequency of the clock. PLL Choose Allows you to specify the PLL used by the clock. Disable Disable each clock output as required. Read Reads the current frequency setting for the oscillator associated with the active tab.
UG-20082 | 2018.02.05 A Safety and Regulatory Information ENGINEERING DEVELOPMENT PRODUCT - NOT FOR RESALE OR LEASE This development kit is intended for laboratory development and engineering use only. This development kit is designed to allow: • Product developers and system engineers to evaluate electronic components, circuits, or software associated with the development kit to determine whether to incorporate such items in a finished product.
A Safety and Regulatory Information UG-20082 | 2018.02.05 A.1 Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system. The socket outlet must be installed near the equipment and must be readily accessible.
A Safety and Regulatory Information UG-20082 | 2018.02.05 Power Cord Requirements The connector that plugs into the wall outlet must be a grounding-type male plug designed for use in your region. It must have marks showing certification by an agency in your region. The connector that plugs into the AC receptacle on the power supply must be an IEC 320, sheet C13, female connector.
A Safety and Regulatory Information UG-20082 | 2018.02.05 Thermal and Mechanical Injury Certain components such as heat sinks, power regulators, and processors may be hot. Heatsink fans are not guarded. Power supply fan may be accessible through guard. Care should be taken to avoid contact with these components. Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes.
A Safety and Regulatory Information UG-20082 | 2018.02.05 Electrostatic Discharge (ESD) Warning A properly grounded ESD wrist strap must be worn during operation/installation of the boards, connection of cables, or during installation or removal of daughter cards. Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling.
UG-20082 | 2018.02.05 B Additional Information B.1 Document Revision History for Intel Cyclone 10 LP FPGA Evaluation Kit User Guide Table 32. Document Revision History for Intel Cyclone 10 LP FPGA Evaluation Kit User Guide Version Description 2018.02.05 • • • • • • • 2017.08.
B Additional Information UG-20082 | 2018.02.05 electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as a result of modifications to the delivered material is the responsibility of the user of this development board. Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide 56 Downloaded from Arrow.com.
