Vol 1

Power Management
36 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows.
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF’ feature which triggers a wakeup
on an interrupt even if interrupts are masked by EFLAGS.IF.
3.2.4 Core C-states
The following are general rules for all core C-states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (for example,
Thread 0 requests C1 while Thread 1 requests C3, resulting in a core C1 state).
• A core transitions to C0 state when:
— An interrupt occurs.
— There is an access to the monitored address if the state was entered via an
MWAIT instruction.
• For core C1, and core C3, an interrupt directed toward a single thread wakes only
that thread. However, since both threads are no longer at the same core C-state,
the core resolves to C0.
• Any interrupt coming into the processor package may wake any core.
3.2.4.1 Core C0 State
The normal operating state of a core where code is being executed.
3.2.4.2 Core C1 State
C1 is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1 state. See the Intel
®
64 and IA-32 Architecture Software Developer’s
Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1 state, it processes bus snoops and snoops from other threads.
Table 3-8. P_LVLx to MWAIT Conversion
P_LVLx MWAIT(Cx) Notes
P_LVL2 MWAIT(C3) The P_LVL2 base address is defined in the PMG_IO_CAPTURE MSR
P_LVL3 MWAIT(C6) C6. No sub-states allowed.