Specification Update

Errata
44 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF99 Intel® QuickData Technology DMA Access to Invalid Memory Address
May Cause System Hang
Problem: When an Intel QuickData Technology DMA access request references an invalid memory
address, the channel generating the request may fail to abort the invalid address
access and cause all channels to hang.
Implication: An Intel QuickData Technology DMA access to an invalid memory address may cause all
channels to hang.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF100 CPUID Faulting is Not Enumerated Properly
Problem: A processor that supports the CPUID-faulting feature enumerates this capability by
setting PLATFORM_INFO MSR (CEH) bit 31. Due to this erratum, the processor
erroneously clears this bit.
Implication: Software that depends upon CPUID faulting will incorrectly determine that the
processor does not support the feature.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF101 TSC is Not Affected by Warm Reset
Problem: The TSC (Time Stamp Counter MSR 10H) should be cleared on reset. Due to this
erratum the TSC is not affected by warm reset.
Implication: The TSC is not cleared by a warm reset. The TSC is cleared by power-on reset as
expected. Intel has not observed any functional failures due to this erratum.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF102 PECI_WAKE_MODE is Always Reported as Disabled
Problem: Due to this erratum, the state of PECI_WAKE_MODE is always reported as disabled.
The PECI (Platform Environment Control Interface) PCS (Package Configuration
Service) WRITE_PECI_WAKE_MODE (0x5) command correctly updates the state of
PECI_WAKE_MODE, but the PECI PCS READ_PECI_WAKE_MODE (0x5) always reports
the PECI_WAKE_MODE as disabled.
Implication: Software depending on the reported value for PECI_WAKE_MODE may not behave as
expected.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF103 Poisoned PCIe* AtomicOp Completions May Return an Incorrect Byte
Count
Problem: A poisoned PCIe AtomicOp request completion may have an incorrect byte count.
Implication: When this erratum occurs, PCIe devices which enable byte count checking will log an
unexpected completion and issue a CTO (Completion Time Out).
Workaround: None identified.
Status: For the affected steppings, see the Table 1, “Summary Table of Changes”.
CF104 Incorrect Speed and De-emphasis Level Selection During DMI
Compliance Testing
Problem: When the DMI port is operating as a PCIe* port, it supports only 2.5 GT/s and 5 GT/s
data rates. According to the PCIe specification, the data rate and de-emphasis level for