Specification Update

Errata
22 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
Workaround: None
Status: For the affected steppings, see the “Summary Table of Changes”.
CF13 A PECI RdPciConfigLocal Command Referencing a Non-Existent Device
May Return an Unexpected Value.
Problem: Configuration reads to nonexistent PCI configuration registers should return
0FFFF_FFFFH. Due to this erratum, when the PECI RdPciConfigLocal command
references a nonexistent PCI configuration register, the value 0000_0000H may be
returned instead of the expected 0FFFF_FFFFH.
Implication: A PECI RdPciConfigLocal command referencing a nonexistent device may observe a
return value of 0000_0000H. Software expecting a return value of 0FFFF_FFFFH to
identify nonexistent devices may not work as expected.
Workaround: Software that performs enumeration via the PECI “RdPciConfigLocal” command should
interpret 0FFFF_FFFFH and 0000_0000H values for the Vendor Identification and
Device Identification Register as indicating a nonexistent device.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF14 The Vswing of the PCIe* Transmitter Exceeds the Specification.
Problem: The PCIe* specification defines a limit for the Vswing (voltage swing) of the differential
lines that make up a lane to be 1200 mV peak-to-peak when operating at 2.5 GT/s and
5 GT/s. Intel has found that the processor’s PCIe* transmitter may exceed this
specification. Peak-to-peak swings on a limited number of samples have been observed
up to 1450 mV.
Implication: For those taking direct measurements of the PCIe* transmit traffic coming from the
processor may detect that the Vswing exceeds the PCIe* specification. Intel has not
observed any functional failures due to this erratum.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF15 PECI Write Requests That Require a Retry Will Always Time Out.
Problem: PECI 3.0 introduces a ‘Host Identification’ field as a way for the PECI host device to
identify itself to the PECI client. This is intended for use in future PECI systems that
may support more than one PECI originator. Since PECI 3.0 systems do not support the
use of multiple originators, PECI 3.0 host devices should zero out the unused Host ID
field. PECI 3.0 also introduces a ‘retry’ bit as a way for the PECI host to indicate to the
client that the current request is a ‘retry’ of a previous read or write operation. Unless
the PECI 3.0 host device zeroes out the byte containing the ‘Host ID & Retry bit’
information, PECI write requests that require a retry will never complete successfully.
Implication: PECI write requests that require a retry may never complete successfully. Instead, they
will return a timeout completion code of 81H for a period ranging from 1 ms to 30 ms if
the ‘RETRY’ bit is asserted.
Workaround: PECI 3.0 host devices should zero out the byte that contains the Host ID and Retry bit
information for all PECI requests at all times including retries.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF16 The Intel
®
QPI Link Status Register link_init_status Field Incorrectly
Reports “Internal Stall Link Initialization” for Certain Stall Conditions.
Problem: The Intel
®
QPI Link Control register (Bus 1, Devices 8, 9, 24; Function 0; Offset 0x44)
bits 17 and 16 allow for the control of the Link Layer Initialization by forcing the link to
stall the initialization process until cleared. The Intel
®
QPI Link Status register (Bus 1,
Device 8, 9, 24; Function 0; Offset 0x48) bits 27:24 report the Link Initialization Status
(link_init_status). The link_init_status incorrectly reports “Internal Stall Link
Initialization” (0001b) for non-Intel
®
QPI link control register, bit[17,16] stall
conditions. The Intel
®
QPI specification does not intend for internal stall conditions to