Specification Update

Summary Table of Changes
10 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF57 XNo Fix
IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
CF58 XNo Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count
Some Transitions
CF59 XNo Fix
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May
be Preempted
CF60 XNo Fix
LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt
Occurs in 64-bit Mode
CF61 XNo Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/
XRSTOR Image Leads to Partial Memory Update
CF62 XNo FixValues for LBR/BTS/BTM Will be Incorrect after an Exit from SMM
CF63 XNo Fix
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a
Translation Change
CF64 XNo FixB0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
CF65 XNo Fix
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a
DTLB Error
CF66 XNo Fix
Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
CF67 XNo FixLER MSRs May be Unreliable
CF68 XNo FixStorage of PEBS Record Delayed Following Execution of MOV SS or STI
CF69 XNo FixPEBS Record Not Updated When in Probe Mode
CF70 XNo FixFaulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
CF71 XNo Fix
#GP on Segment Selector Descriptor That Straddles Canonical Boundary
May Not Provide Correct Exception Error Code
CF72 XNo FixAPIC Error “Received Illegal Vector” May Be Lost
CF73 XNo Fix
Changing the Memory Type for an In-Use Page Translation May Lead to
Memory-Ordering Violations
CF74 XNo Fix
Reported Memory Type May Not be Used to Access the VMCS and Referenced
Data Structures
CF75 XNo Fix
LBR, BTM or BTS Records May have Incorrect Branch From Information After
an Enhanced Intel SpeedStep® Technology/T-state/S-state/C1E Transition
or Adaptive Thermal Throttling
CF76 XNo Fix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access
Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in
64-bit Mode
CF77 XNo Fix
VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported
Field in VMCS
CF78 XNo Fix
An Unexpected PMI May Occur After Writing a Large Value to
IA32_FIXED_CTR2
CF79 XNo Fix
A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in
Certain Conditions
CF80 XNo Fix
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch
Instructions
CF81 XNo Fix
Interrupt From Local APIC Timer May Not be Detectable While Being
Delivered
CF82 XNo Fix
PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate
with 32-bit Length Registers
CF83 XNo Fix
During Package Power States Repeated PCIe* and/or DMI L1 Transitions May
Cause a System Hang
Table 1. Summary Table of Changes (Sheet 3 of 6)
No.
Stepping
Status Errata
D1