Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 9
Figures
1-1 Dual-Processor System Block Diagram ..............................................................19
2-1 MCH Interface Signals ........................................................................................ 22
3-1 PAM Registers ....................................................................................................57
3-2 Memory Socket Rows Description ...................................................................... 58
4-1 System Memory Address Map ..........................................................................145
4-2 Detailed Memory Address Map (Below 1 MB) .................................................. 146
4-3 Detailed Extended Memory Address Map (1 MB to 4 GB)................................ 147
7-1 MCH Ballout Showing 1005 Pins (Top View) ....................................................183
7-2 MCH Ballout (Left Half of Top View) .................................................................184
7-3 MCH Ballout (Right Half of Top View) ...............................................................185
7-4 Package Dimensions (Bottom View) .................................................................204
7-5 Package Dimensions (Top and Side Views) .....................................................205
8-1 XOR Test Tree Chain........................................................................................215
Tables
1-1 Supported Memory Modes ..................................................................................18
1-2 DIMM Support .....................................................................................................18
2-1 Host Interface Signals .........................................................................................23
2-2 DDR Channel A Signals ......................................................................................26
2-3 DDR Channel B Signals ......................................................................................29
2-4 Hub Interface_A Signals......................................................................................32
2-5 Hub Interface_B Signals......................................................................................32
2-6 AGP Arbitration Signals.......................................................................................33
2-7 AGP Address/ Data Signals ................................................................................34
2-8 AGP Command/ Control Signals......................................................................... 35
2-9 Clocks, Reset, and Miscellaneous Signals..........................................................37
3-1 MCH Logical Configuration Resources ...............................................................40
3-2 Chipset Host Controller Register Address Map (D0:F0) .....................................45
3-3 PAM Associated Attribute Bits.............................................................................57
3-4 Chipset Host RAS Controller Register Address Map (D0:F1) ............................. 79
3-5 PCI-to-AGP Bridge Register Address Map (D1:F0) ............................................98
3-6 Hub Interface_B PCI-to-PCI Register Map (D2:F0) ..........................................122
3-7 Hub Interface_B – PCI-to-PCI Bridge Error Reporting Register Address Map
(D2:F1)134
4-1 SMM Address Range ........................................................................................153
5-1 Key Differences Between AGP 3.0 and AGP 2.0 Signaling Modes ..................159
5-2 AGP 3.0 Downshift Mode Parameters ..............................................................160
5-3 AGP 3.0 and AGP 2.0 Support Command Types ............................................. 161
5-4 AGP Summary of Transaction Coherency ........................................................161
5-5 Data Rates and Signaling Levels Supported by the MCH................................. 162
5-6 DRAM Terminology ...........................................................................................165
5-7 Supported System Bus and Memory Interface Configurations .........................166
5-8 Maximum Supported Memory Configurations ...................................................167
5-9 Memory per DIMM at Each DRAM Density.......................................................167
5-10 Clock Connections ............................................................................................168
5-11 ACPI State to Clock State Mapping ..................................................................171
6-1 Absolute Maximum Ratings...............................................................................173
6-2 DC Characteristics Functional Operating Range ..............................................173