Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 83
Register Description
3.6.8 MLT—Master Latency Timer Register (D0:F1)
Address Offset: 0Dh
Default Value: 00h
Sticky No
Attribute: RO
Size: 8 bits
Device 0 in the MCH is not a PCI master; therefore, this register is not implemented.
3.6.9 HDR—Header Type Register (D0:F1)
Address Offset: 0Eh
Default Value: 01h
Sticky No
Attribute: RO
Size: 8 bits
3.6.10 SVID—Subsystem Vendor Identification Register (D0:F1)
Address Offset: 2Ch
Default Value: 0000h
Sticky No
Attribute: R/WO
Size: 16 bits
This value is used to identify the vendor of the subsystem.
3.6.11 SID—Subsystem Identification Register (D0:F1)
Address Offset: 2E–2Fh
Default Value: 0000h
Sticky No
Attribute: R/WO
Size: 16 bits
This value is used to identify a particular subsystem.
Bits
Default,
Access
Description
7:0 Reserved
Bits
Default,
Access
Description
7:0
01h
RO
PCI Header (HDR). This read only field always returns 01h to indicate that device 1 is a
single-function device with bridge header layout.
Bits
Default,
Access
Description
15:0
0000h
R/WO
Subsystem Vendor ID (SUBVID). This field should be programmed during boot-up to
indicate the vendor of the system board. After it has been written once, it becomes read
only.
Bits
Default,
Access
Description
15:0
0000h
R/WO
Subsystem ID (SUBID). This field should be programmed during BIOS initialization.
After it has been written once, it becomes read only.