Hub Datasheet

Intel

E7505 Chipset MCH Datasheet 69

3.5.25 ESMRAMC—Extended System Management RAM Control

Address Offset: 9Eh

Default Value: 38h

Attribute: RO, R/W/L, R/WC

Size: 8 bits

The Extended SMRAM register controls the configuration of Extended SMRAM space. The

Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory

space that is above 1 MB.

Bits

Default,

Access

Description

R/W/L

Enable High SMRAM (H_SMRAME). This bit controls the SMM memory space location

(i.e., above 1 MB or below 1 MB)

0 = Disable.

1 = Enable. When G_SMRAME is 1 and H_SMRAME is set to 1, the high SMRAM

memory space is enabled. SMRAM accesses within the range 0FEDA_0000h to

0FEDA_FFFFh are remapped to DRAM addresses within the range 000A0000h to

000BFFFFh.

NOTE: Once D_LCK is set, this bit becomes read only.

R/WC

Invalid SMRAM Access (E_SMERR).

1 = This bit is set when processor has accessed the defined memory ranges in

Extended SMRAM (High Memory and T-segment) while not in SMM space and with

the D-OPEN bit = 0.

NOTE: The software must write a 1 to this bit to clear it.

2:1

00b

R/W/L

TSEG Size (TSEG_SZ). This field selects the size of the TSEG memory block if

enabled. Memory from the top of DRAM space (TOLM – TSEG_SZ) to TOLM is

partitioned away so that it may only be accessed by the processor interface, and only

then when the SMM bit is set in the request packet. Non-SMM accesses to this memory

region are sent to the hub interface when the TSEG memory block is enabled.

00 = (TOLM–128 KB) to TOLM

01 = (TOLM – 256 KB) to TOLM

10 = (TOLM – 512 KB) to TOLM

11 = (TOLM – 1 MB) to TOLM

NOTE: Once D_LCK is set, these bits become read only.

R/W/L

TSEG Enable (TSEG_EN). Enabling of SMRAM memory for Extended SMRAM space

only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the

appropriate physical address space.

NOTE: Once D_LCK is set, this bit becomes read only.