Hub Datasheet

Signal Description
26 Intel
®
E7505 Chipset MCH Datasheet
2.2 DDR Channel A Signals
Table 2-2. DDR Channel A Signals (Sheet 1 of 3)
Signal Name Type Description
CB_A[7:0]
I/O
SSTL-2
ECC Data bits: These signals are the 8-bit ECC data, running at 2x data
rate. The data is source synchronous using the DQS strobes.
DQ_A[63:0]
I/O
SSTL-2
Data: These signals are the 64-bit data bus, running at 2x data rate. The
data is source synchronous using the DQS strobes.
DQS_A[17:0]
I/O
SSTL-2
Data Strobes: These signals provide the timing information for the data and
ECC bits. They are driven by the source of the data. Nine signals are
required for x8 and x16 RAMs; eighteen are required for x4 RAMs. When
accessing x8 or x16 DRAM rows, DQS_A[17:9] are driven low during write
cycles since these pins will be connected to the DM (data mask) inputs of
the DRAMs on the DIMM.
CMDCLK_A[7:0]
O
CMOS
Differential Clock: These signals are outputs to the DIMMs. Commands
are referenced to the rising edge of CMDCLK_x and the falling edge of
CMDCLK_x#; one per DIMM for registered DIMMs, 3 per DIMM for
unbuffered DIMMs.
The mapping is shown in the following table:
• CK0/CK0# are at pins 137 and 138 of the DIMM.
• CK1/CK1# are at pins 16 and 17 of the DIMM.
• CMDCLK_A6 is multiplexed with CS_A5#.
CMDCLK_A[7:0]#
O
CMOS
Differential Clock: These signals are outputs to the DIMMs. Commands
are referenced to the rising edge of CMDCLK_x and the falling edge of
CMDCLK_x#; one per DIMM for registered DIMMs, 3 per DIMM for
unbuffered DIMMs.
• CMDCLK_A6# is multiplexed with CS_A4#.
Signal 2 DIMM 3 DIMM
CMDCLK_A7 DIMM 1 CK2
CMDCLK_A6/CS_A5# DIMM 0 CK2
CMDCLK_A5 DIMM 1 CK1
CMDCLK_A4 DIMM 0 CK1
CMDCLK_A3
CMDCLK_A2 DIMM 2 CK0
CMDCLK_A1 DIMM 1 CK0 DIMM 1 CK0
CMDCLK_A0 DIMM 0 CK0 DIMM 0 CK0
Signal 2 DIMM 3 DIMM
CMDCLK_A7# DIMM 1 CK2#
CMDCLK_A6#/CS_A4# DIMM 0 CK2#
CMDCLK_A5# DIMM 1 CK1#
CMDCLK_A4# DIMM 0 CK1#
CMDCLK_A3#
CMDCLK_A2# DIMM 2 CK0#
CMDCLK_A1# DIMM 1 CK0# DIMM 1 CK0#
CMDCLK_A0# DIMM 0 CK0# DIMM 0 CK0#