Hub Datasheet

3
Working page only. Do not distribute.
3.6.30 DRAM_UELOG_ADD—DRAM First Uncorrectable Memory Error Ad-
dress Register (D0:F1)97
3.6.31 DRAM_CELOG_SYNDROME—DRAM First Correctable
Memory Error Register (D0:F1) ........................................................97
3.7 PCI-to-AGP Bridge Registers (Device 1, Function 0) ....................................98
3.7.1 VID1—Vendor Identification Register (D1:F0) ..................................99
3.7.2 DID1—Device Identification Register (D1:F0) ..................................99
3.7.3 PCICMD1—PCI Command Register (D1:F0) .................................100
3.7.4 PCISTS1—PCI Status Register (D1:F0).........................................101
3.7.5 RID1—Revision Identification Register (D1:F0)..............................102
3.7.6 SUBC1—Sub-Class Code Register (D1:F0)...................................102
3.7.7 BCC1—Base Class Code Register (D1:F0) ...................................102
3.7.8 MLT1—Master Latency Timer (Scratch Pad) Register (D1:F0) ......103
3.7.9 HDR1—Header Type Register (D1:F0) ..........................................103
3.7.10 APBASELO—AGP Aperture Base Address Register (D1:F0)........104
3.7.11 PBUSN1—Primary Bus Number Register (D1:F0) .........................105
3.7.12 SBUSN1—Secondary Bus Number Register (D1:F0) .................... 105
3.7.13 SUBUSN1—Subordinate Bus Number Register (D1:F0) ...............105
3.7.14 SMLT1—Secondary Bus Master Latency Timer Register (D1:F0) .106
3.7.15 IOBASE1—I/O Base Address Register (D1:F0) .............................106
3.7.16 IOLIMIT1—I/O Limit Address Register (D1:F0) ..............................107
3.7.17 SSTS1—Secondary Status Register (D1:F0) .................................108
3.7.18 MBASE1—Memory Base Address Register (D1:F0)......................109
3.7.19 MLIMIT1—Memory Limit Address Register (D1:F0).......................110
3.7.20 PMBASE1—Prefetchable Memory Base Address Register (D1:F0) ....
111
3.7.21 PMLIMIT1—Prefetchable Memory Limit Address Register (D1:F0)112
3.7.22 CAPPTR—Capabilities Pointer Register (D1:F0) ...........................112
3.7.23 BCTRL1—Bridge Control Register (D1:F0) ....................................113
3.7.24 ERRCMD1—Error Command Register (D1:F0) .............................114
3.7.25 ERRSTS1—Error Status Register (D1:F0) ..................................... 115
3.7.26 AGPCAPID1—AGP Capability Identifier Register (D1:F0) ............. 115
3.7.27 AGPSTAT1—AGP Status Register (D1:F0) ...................................116
3.7.28 AGPCMD—AGP Command Register (D1:F0)................................117
3.7.29 AGPCTRL1—AGP Control Register (D1:F0)..................................119
3.7.30 APSIZE1—AGP Aperture Size Register (D1:F0)............................120
3.7.31 ATTBASE1—AGP GART Pointer Register (D1:F0) .......................121
3.8 Hub Interface_B PCI-to-PCI Bridge Registers (Device 2, Function 0).........122
3.8.1 VID2—Vendor Identification Register (D2:F0) ................................123
3.8.2 DID2—Device Identification Register (D2:F0) ................................123
3.8.3 PCICMD2—PCI Command Register (D2:F0) .................................124
3.8.4 PCISTS2—PCI Status Register (D2:F0).........................................125
3.8.5 RID2—Revision Identification Register (D2:F0)..............................126
3.8.6 SUBC2—Sub-Class Code Register (D2:F0)...................................126
3.8.7 BCC2—Base Class Code Register (D2:F0) ...................................126
3.8.8 MLT2—Master Latency Timer (Scratch Pad) Register (D2:F0) ......127
3.8.9 HDR2—Header Type Register (D2:F0) ..........................................127
3.8.10 PBUSN2—Primary Bus Number Register (D2:F0) .........................127
3.8.11 SBUSN2—Secondary Bus Number Register (D2:F0) .................... 128
3.8.12 SUBUSN2—Subordinate Bus Number Register (D2:F0) ...............128
3.8.13 IOBASE2—I/O Base Address Register (D2:F0) .............................129
3.8.14 IOLIMIT2—I/O Limit Address Register (D2:F0) ..............................129