Hub Datasheet

168 Intel
®
E7505 Chipset MCH Datasheet
Functional Description
5.5.6 Intel
®
x4 SDDC Technology ECC
The MCH supports Intel
®
x4 Single Device Data Correction (x4 SDDC) technology ECC. The
ECC code spans 144 bits of data. ECC may be disabled by the System BIOS. No performance gain
is achieved.
The x4 SDDC technology ECC performs the following:
• Corrects any number of errors contained in a 4-bit naturally aligned nibble.
• Detects all errors contained entirely with two 4-bit naturally aligned nibbles.
• Corrects errors caused by a complete failure of a x4 SDRAM part.
5.5.7 Memory Thermal Management
The MCH provides a thermal management method that selectively reduces reads and writes to
DRAM when the access rate crosses the allowed thermal threshold. Read and write thermal
management operate independently, and have their own 64-bit register to control operation.
Memory reads typically causes power dissipation in the DRAM chips, while memory writes
typically cause power dissipation in the MCH.
Determining When to Thermal Manage
Thermal management may be enabled by one of two mechanisms:
• Software forcing throttling via the SRT (SWT) bit.
• Counter Mechanism.
5.5.8 Clock Generation
The MCH drives the clocks to the DIMMs. Unbuffered DIMMs require 3 clock pair per DIMM
while Registered DIMMs require one clock pair per DIMM. A 2-DIMM slot unbuffered
motherboard requires 6 clock pair (per channel), while the 3-DIMM slot Registered motherboard
requires 3 clock pair (per channel). Table 5-10 shows the clock connections.
Table 5-10. Clock Connections
Signal 2 DIMM MB 3 DIMM MB
CMDCLK7, CMDCLK7# DIMM1 CK2, CK2# No connect
CMDCLK6, CMDCLK6# / CS[5:4]# DIMM0 CK2, CK2# DIMM 2 CS[1:0]
CMDCLK5, CMDCLK5# DIMM1 CK1, CK1# No connect
CMDCLK4, CMDCLK4# DIMM0 CK1, CK1# No connect
CMDCLK3, CMDCLK3# No connect No connect
CMDCLK2, CMDCLK2# No connect DIMM2 CK0
CMDCLK1, CMDCLK1# DIMM1 CK0, CK0# DIMM1 CK0
CMDCLK0, CMDCLK0# DIMM0 CK0, CK0# DIMM0 CK0