Hub Datasheet
116 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.27 AGPSTAT1—AGP Status Register (D1:F0)
Address Offset: 64–67h
Default Value: see table below
Attribute: RO
Size: 32 bits
This register reports AGP device capability/status. Read by drivers.
Bits
Default,
Access
Description
31:24
1Fh
RO
Request Queue (RQ). Hardwired to 1Fh. This field contains the maximum number of
AGP command requests the MCH is configured to manage.
1Fh = 32 outstanding AGP command requests maximum can be handled by the MCH.
23:16 Reserved
15:13
010b
RO
Async Request Size (ARQSZ). This value is LOG2 of the optimum asynchronous
request size in bytes minus 4 to be used with the MCH.
010 = 64 byte MCH cache line size.
12:10
000b
RO
Calibration Period.
000 = 4 ms
9
1b
RO
Side Band Addressing Support (SBA). Hardwired to 1. The MCH supports side band
addressing. AGP 8x requires sideband addressing. This bit is reserved in the AGP
Specification 3.0, and read only as a 1 to be compatible with the Device 0 register.
8
0b
RO
Inside the Aperture GART entry coherency (ITA_C OH). Hardwired to 0. The MCH
does not support coherency based on the coherency bit in the GART entries.
7
0b
RO
64-bit GART support (GART64). Hardwired to 0. The MCH supports 32 bit GART
entries only. The 32 bit GART entries allows 36 bit support.
6
0b
RO
Host Translation support (HTRANS#). Hardwired to 0. The MCH supports translating
accesses from the host processor through the aperture.
5
0b
RO
Greater Than Four Gigabyte Support (GT4GIG). Hardwired to 0. The MCH does not
support addresses greater than 4-GB AGP.
4
1b
RO
Fast Write Support (FW). Hardwired to 1. The MCH supports Fast Writes from the
processor-to-AGP master. This bit is reserved in the AGP Specification 3.0, and read
only as a 1 to be compatible with the Device 0 register.
3
x
RO
AGP 3.0 mode. This bit is set by the hardware on reset based on the AGP 8x detection
via the VREF Comparator.
0 = AGP 2.0 signaling mode (1.5 V).
1 = Graphics card is AGP 8x mode
2:0
111b
or 01x
RO
Data Rate Support (RATE). The value of this field is determined by the AGP 3.0
signaling mode bit above. In AGP 3.0 signaling mode (AGP 3.0 signaling mode = 1)
these bits are 01X, indicating that 3.0 signaling mode is supported. Bit 0 is determined
by BIOS. In AGP 2.0 signaling mode, these bits are 111 indicating that 1x, 2x, and 4x
modes are all supported.
NOTE: Signaling Mode is determined by bit 3 (AGP 3.0 signaling mode, above)
BIt 2 Bit 1 Bit 0
2.0 Signaling (1.5 V)
Data Rate 4x 2x 1x
MCH Value 1 (supported) 1 (supported) 1 (supported)
3.0 Signaling (0.8 V)
Data Rate reserved 8x 4x
MCH Value 0 1 (supported) Programmable