Hub Datasheet

108 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.17 SSTS1—Secondary Status Register (D1:F0)
Address Offset: 1E–1Fh
Default Value: 02A0h
Attribute: R/W
Size: 16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the
secondary side (i.e., AGP side) of the virtual PCI-to-PCI bridge in the MCH.
Note: Software writes a 1 to clear bits that are set.
Bits
Default,
Access
Description
15
0b
R/WC
Detected Parity Error (DPE).
0 = No parity error detected in the address or data phase of AGP bus transactions.
1 = MCH detected a parity error in the address or data phase of AGP bus transactions.
14
0b
R/WC
Received System Error (RSE).
0 = No SERR# assertion detected.
1 = MCH detects SERR# assertion on the secondary side of this device.
13
0b
R/WC
Received Master Abort Status (RMAS).
0 = MCH Does Not terminate a Host-to-AGP with an unexpected master abort.
1 = MCH terminates a Host-to-AGP with an unexpected master abort.
12
0b
R/WC
Received Target Abort Status (RTAS).
0 = MCH-initiated transaction on AGP is Not terminated with a target abort.
1 = MCH-initiated transaction on AGP is terminated with a target abort.
11
0b
RO
Signaled Target Abort Status (STAS). Hardwired to 0. The MCH does not generate
target abort on AGP.
10:9
01b
RO
DEVSEL# Timing (DEVT). Hardwired to 01. This 2-bit field indicates the timing of the
DEVSEL# signal when the MCH responds as a target on AGP; a value of 01(medium)
indicate the time when a valid DEVSEL# can be sampled by the initiator of the PCI
cycle.
8
0b
RO
Master Data Parity Error Detected (DPD). Hardwired to 0. MCH does not implement
G_PERR# signal on AGP.
7
1b
RO
Fast Back-to-Back (FB2B). Hardwired to 1. MCH, as a target, supports fast back-to-
back transactions on AGP.
6 Reserved
5
1b
RO
66/60 MHz capability (CAP66). Hardwired to 1. This indicates that the AGP bus is
capable of 66 Mhz operation.
4:0 Reserved