Datasheet

Datasheet 191
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.57 LE1A—Link Entry 1 Address
B/D/F/Type: 0/1/0/MMR
Address Offset: 158-15Fh
Default Value: 0000000000000000h
Access: RO, RWO
Size: 64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
6.58 PESSTS—PCI Express* Sequence Status
B/D/F/Type: 0/1/0/MMR
Address Offset: 218–21Fh
Default Value: 0000000000000FFFh
Access: RO
Size: 64 bits
PCI Express status reporting that is required by the PCI Express specification.
Bit Access
Default
Value
Description
63:32 RO
0000000
0h
Reserved
31:12 RWO 00000h
Link Address (LA): Memory mapped base address of the RCRB that is the
target element (Egress Port) for this link entry.
11:0 RO 000h Reserved
Bit Access
Default
Value
Description
63:60 RO 0h Reserved
59:48 RO 000h
Next Transmit Sequence Number (NTSN): Value of the NXT_TRANS_SEQ
counter. This counter represents the transmit Sequence number to be applied to
the next Transaction Layer Packet to be transmitted onto the Link for the first
time.
47:44 RO 0h Reserved
43:32 RO 000h
Next Packet Sequence Number (NPSN): Packet sequence number to be
applied to the next Transaction Layer Packet to be transmitted or re-transmitted
onto the Link.
31:28 RO 0h Reserved
27:16 RO 000h
Next Receive Sequence Number (NRSN): This is the sequence number
associated with the Transaction Layer Packet that is expected to be received
next.
15:12 RO 0h Reserved
11:0 RO FFFh
Last Acknowledged Sequence Number (LASN): This is the sequence
number associated with the last acknowledged Transaction Layer Packet.