Datasheet

Features
80 Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
7.4.2 Scratch EEPROM
Also available in the memory component on the processor SMBus is an EEPROM which may be
used for other data at the system or processor vendor’s discretion. The data in this EEPROM, once
programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a
weak pull-down (10 kΩ) to allow the EEPROM to be programmed in systems with no
implementation of this signal. The Scratch EEPROM resides in the upper half of the memory
component (addresses 80 - FFh). The lower half comprises the Processor Information ROM
(addresses 00 - 7Fh), which is permanently write-protected by Intel.
7.4.3 PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIROM) responds to two SMBus packet types: Read Byte and
Write Byte. However, since the PIROM is write-protected, it will acknowledge a Write Byte
command but ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands. Table 7-3 diagrams the Read Byte command. Table 7-4 diagrams the Write Byte
command. Following a write cycle to the scratch ROM, software must allow a minimum of 10 ms
before accessing either ROM of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read bit,
‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ represents a negative
acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or
Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host controller. In
the tables, the data addresses indicate 8 bits. The SMBus host controller should transmit 8 bits with
the most significant bit indicating which section of the EEPROM is to be addressed: the Processor
Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
7Ah
8 Additional Processor
Feature Flags
[7] = Reserved
[6] = Reserved
[5] = Enhanced Halt State
[4] = Intel
®
Virtualization Technology
[3] = Execute Disable
[2] = Intel
®
64 architecture
[1] = Thermal Monitor 2
[0] = Enhanced Intel SpeedStep
®
Technology
7B-7Ch
16 Thermal Adjustment Factors
(Pending)
[15:8] Measurement Correction Factor
[7:0] Temperature Target
7D- 7Eh 16 Reserved Reserved
7Fh 8 Checksum 1 byte checksum
Table 7-2. Processor Information ROM Format (Sheet 3 of 3)
Offset/Section
# of
Bits
Function Notes
Table 7-3. Read Byte SMBus Packet
S
Slave
Address
Write A
Command
Code
AS
Slave
Address
Read A Data /// P
17-bits 1
18-bits1 1 7-bits 1 1 8-bits 1 1