Vol 2

4 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
4.6 iMC Interface ....................................................................................................37
4.6.1 HA to MC Interface .................................................................................37
4.6.2 Target Address Decode (TAD)...................................................................37
5 iMC Functional Description.......................................................................................39
5.1 Overview..........................................................................................................39
5.2 Operation .........................................................................................................40
5.2.1 Overview...............................................................................................40
5.2.2 Logical and Physical Channels...................................................................41
5.2.3 Lockstep................................................................................................41
5.2.4 Independent Channel Mode......................................................................41
5.3 Memory Address Decode.....................................................................................41
5.3.1 Summary of Address Translation ..............................................................42
5.3.2 DRAM Maintenance Operations .................................................................42
5.3.3 Refresh .................................................................................................42
6 IIO Functional Description.......................................................................................45
6.1 Integrated I/O Module Overview..........................................................................45
6.1.1 PCI Express* Features.............................................................................45
6.1.2 Direct Media Interface (DMI2) Features .....................................................46
6.1.3 PCIe* 3.0 ..............................................................................................46
6.1.4 Intel
®
I/O Acceleration Technology (Intel
®
I/OAT) 4....................................46
6.1.5 Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O
(Intel
®
VT-d 2) Features..........................................................................46
6.1.6 Power Management Support Features........................................................46
6.1.7 Security Features....................................................................................46
6.2 PECI and JTAG ..................................................................................................47
6.2.1 PECI .....................................................................................................47
6.2.2 JTAG.....................................................................................................47
6.3 PCI Express and DMI Interfaces...........................................................................47
6.3.1 PCI Express ...........................................................................................47
6.3.2 Speed Support .......................................................................................47
6.3.3 PCI Express Link Characteristics - Bifurcation, Link
Training, Downgrading and Lane Reversal Support......................................47
6.3.4 Technologies Supported over PCI Express..................................................49
6.3.5 32/64 Bit Addressing...............................................................................49
6.3.6 Direct Media Interface (DMI)....................................................................49
6.4 Power Management............................................................................................49
6.5 Intel Virtualization Technology.............................................................................49
7 Reliability, Availability, Serviceability, and Manageability ........................................51
7.1 RASM Overview.................................................................................................51
7.1.1 Error Sources.........................................................................................52
7.1.2 Error Classification..................................................................................52
7.1.3 RASM Feature Summary..........................................................................53
7.2 Error Detection and Correction ............................................................................54
7.3 Error Reporting via Machine Check Architecture .....................................................54
7.3.1 Viral Alert..............................................................................................54
7.4 Memory RAS.....................................................................................................55
7.4.1 Features and Capabilities.........................................................................55
7.4.2 Write Data Buffer Parity...........................................................................55
7.4.3 Mirroring ...............................................................................................55
7.4.4 Sparing and Scrubber..............................................................................55
7.4.5 Single Device Data Correction (SDDC).......................................................56
7.4.6 Double Device Data Correction (DDDC)......................................................56
7.4.7 +1 Bit Correction Beyond Device Correction ...............................................56
7.4.8 PECI Write Accessibility to iMC Registers....................................................56
7.4.9 iMC Error Handling..................................................................................56