Vol 2

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 207
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.20 PLIM
Prefetchable Memory Limit Register.
14.2.21 PBASU
Prefetchable Memory Base Upper 32 bits.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0 (PCIe* Mode)
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x26
Bit Attr Default Description
15:4 RW 0x0
prefetchable_memory_limit_address:
Corresponds to A[31:20] of the prefetchable memory address range’s limit
address of the PCI Express port. See also the PLIMU register description.
3:0 RO 0x1
prefetchable_memory_limit_address_capability:
IIO sets this field to 01h to indicate 64bit capability.
Type: CFG PortID: N/A
Bus: 0 Device: 0Function:0 (PCIe* Mode)
Bus: 0 Device: 2Function:0-3
Bus: 0 Device: 3Function:0-3
Offset: 0x28
Bit Attr Default Description
31:0 RW 0xffffffff
prefetchable_upper_32_bit_memory_base_address:
Corresponds to A[63:32] of the prefetchable memory address range’s base
address of the PCI Express port. See also the PLIMU register description.