Vol 1

Overview
16 Intel® Xeon® Processor E7-8800/4800/2800 v2 Product Family
Datasheet Volume One, February 2014
APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
System Management Interrupt (SMI), SCI, and SERR error indication
Static lane numbering reversal support
Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4 Intel® QuickPath Interconnect (Intel® QPI)
Compliant with Intel QuickPath Interconnect v1.1 standard packet formats
Implements three full width Intel QPI ports
Full width port includes 20 data lanes and 1 clock lane
64 byte cache-lines
Home snoop based coherency
•4-bit Node ID
46-bit physical addressing support
No Intel QuickPath Interconnect bifurcation support
Differential signaling
Forwarded clocking
Up to 8.0 GT/s data rate (up to 16 GB/s per direction peak bandwidth per port)
Ports 0 & 1 run at same operational frequency
Port 2 may run at a separate operational frequency
Reference Clock is 100 MHz
Slow boot speed initialization at 50 MT/s
Common reference clocking (same clock generator for both sender and receiver)
Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability
Polarity and Lane reversal
1.2.5 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The PECI interface is based on revision
3.0 of the RS - Platform Environment Control Interface (PECI) Specification.
Supports operation at up to 2 Mbps data transfers
Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
Services include CPU thermal and estimated power information, control functions
for power limiting, P-state and T-state control, and access for Machine Check
Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
PECI address determined by SOCKET_ID configuration
Single domain (Domain 0) is supported