Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 35
Signal Description
2.6.3 AGP Command/Control Signals
Table 2-8. AGP Command/ Control Signals (Sheet 1 of 2)
Signal Name Type Description
PIPE# (2.0),
DBI_HI (3.0)
I/O
AGP
Pipelined Read: This signal is asserted by the current master to indicate a full
width address is to be enqueued by the target. The master enqueues one
request each rising clock edge while PIPE# is asserted. When PIPE# is
deasserted, no new requests are re-queued across the AD bus.
PIPE# may be used in AGP 2.0 signaling modes, but is not permitted by the
AGP 3.0 specification. When operating in AGP 3.0 signaling mode, the PIPE#
signal is used for dynamic bus inversion.
PIPE# is a sustained tri-state signal from the master (graphics controller) and is
an input to the MCH.
Dynamic Bus Inversion Hi (AGP 3.0 signaling mode). This signal goes along
with GAD[31:16] to indicate whether GAD[31:16] must be inverted on the
receiving end.
• DBI_HI = 0 GAD[31:16] is not inverted so receiver may use as is
• DBI_HI = 1 GAD[31:16] is inverted so receiver must invert before use.
• The AD_STBF1 and AD_STBS1 strobes are used with DBI_HI.
In AGP 3.0 signaling mode (4x data rate), DBI is disabled by the MCH while
transmitting (data never inverted and DBI_HI driven low) but is enabled when
receiving data. For 8x data rate, DBI is enabled when transmitting and receiving
data.
SBA[7:0] (2.0),
SBA[7:0]# (3.0)
I
AGP
Sideband Address: This bus provides an additional bus to pass address and
command to the MCH from the AGP master.
NOTE: In AGP 2.0 signaling mode, when sideband addressing is disabled,
these signals are isolated. When sideband addressing is enabled,
internal pull-ups are enabled to prevent indeterminate values on them
in cases where the Graphics Card may not have its SBA[7:0] output
drivers enabled yet.
SB_STB (2.0),
SB_STBF (3.0)
I
AGP
Sideband Strobe: In AGP 2.0 signaling mode, this signal is used to provide
timing for 4x clocked data.
Sideband Strobe First: In AGP 3.0 signaling mode this signal strobes the first
and all odd numbered data items with a low-to-high transition.
SB_STB# (2.0),
SB_STBS (3.0)
I
AGP
Sideband Strobe Complement: The differential complement to the SB_STB
signal. In AGP 2.0 signaling mode, it is used to provide timing for 4x clocked
data in.
Sideband Strobe Second: In AGP 3.0 signaling mode this signal strobes the
second and all even numbered data items with a low-to-high transition.
GFRAME# (2.0),
GFRAME (3.0)
I
AGP
FRAME: This signal is driven by the current master to indicate the beginning
and duration of a standard PCI protocol (“Frame Based”) transaction and during
fast writes. It is not used, and must be inactive during AGP transactions.
GIRDY# (2.0),
GIRDY (3.0)
I/O
s/t/s
AGP
Initiator Ready: This signal is used for both GFRAME(#) based and AGP
transactions. During AGP transactions, it indicates the AGP compliant master is
ready to provide all write data for the current transaction. Once IRDY# is
asserted for a write operation, the master is not allowed to insert wait-states.
The assertion of IRDY# (IRDY) for reads indicates that the master is ready to
transfer to a subsequent block (32 bytes) of read data. The master is never
allowed to insert a wait-state during the initial data transfer (32 bytes) of a read
transaction. However, it may insert wait-states after each 32-byte block is
transferred.
NOTE: There is no GFRAME(#) – GIRDY(#) relationship for AGP transactions.