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158 Intel
®
E7505 Chipset MCH Datasheet
Functional Description
5.4 AGP 8x Interface
The MCH supports AGP 8x with backwards compatibility to AGP 4x. The electrical signal levels
supported by the MCH for the AGP 8x interface are 0.8 V levels for 8x, 4x (AGP 3.0) transfers.
The MCH can also operate in 4x, 2x, and 1x (AGP 2.0) modes: these modes are only at 1.5 V
signal levels.
Note: The MCH does not support 3.3 V signal levels.
The MCH has a 32-deep AGP request queue that is used for Asynchronous modes. The MCH
integrates two fully-associative 10 entry Translation Look-aside Buffers; one for reads and one for
writes.
5.4.1 Selecting between AGP 3.0 and AGP 2.0 Signaling Modes
The MCH supports both AGP 3.0 and AGP 2.0 specifications allowing a “Universal AGP 8x
motherboard” implementation. The AGP 3.0 or AGP 2.0 signaling mode setting is determined by
the type of graphic card installed in the system. The mode determination is decided during RESET
by a hardware mechanism (see Section 5.4.9).
Note: The configured AGP mode determines the electrical signal levels and cannot be dynamically
changed once the system power ups.
5.4.2 Dynamic Bus Inversion (DBI)
To mitigate the effects of simultaneous switching outputs, AGP 3.0 adopts a technique called
Dynamic Bus Inversion (DBI) to limit the maximum number of simultaneous transitions on source
synchronous data transfers. DBI impacts only GAD[31:0] and is used during source synchronous
and common clock transfers. Two new signals are defined to support DBI. DBI_LO and DBI_HI
are used to implement DBI on GAD[15:0] and GAD[31:16], respectively.
When the number of bit transitions in GAD[15:0] (or GAD[31:16]) from one source synchronous
period to the next exceeds eight, the entire field is inverted by the transmitter to limit the maximum
transitions to eight. For example, if GAD[15:0] changes from FF10h in source synchronous cycle
A to 0000h in source synchronous cycle B, the DBI mechanism is triggered in cycle B; this inverts
GAD[15:0] to produce FFFFh. In this example, the number of transitions without DBI is nine; the
number with DBI is seven. To signal the receiver that GAD[15:0] are inverted in cycle B, DBI_LO
is asserted high. The same mechanism is used on GAD[31:16]. DBI_HI is used to indicate the
inversion. The receiver samples DBI_HI and DBI_LO to determine whether to invert GAD[31:0]
before using it.
A similar technique applies to common clock and frame-based (PCI) address and data transfers. In
these instances, DBI applies to transitions from one common clock period to the next.
DBI is supported when operating in 8x speed and in AGP 3.0 signaling mode. During 4x speed
transfers or frame-based PCI transfers in the same signaling mode, DBI is not supported in
transmit but is supported in receive. DBI is not supported when in AGP 2.0 or AGP 1.0 signaling
modes.