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Intel

E7505 Chipset MCH Datasheet 111

3.7.20 PMBASE1—Prefetchable Memory Base Address Register

(D1:F0)

Address Offset: 24–25h

Default Value: FFF0h

Attribute: R/W, RO

Size: 16 bits

This register controls the processor-to-AGP prefetchable memory accesses routing based on the

following formula:

PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A31:20

of the 32-bit address. The bottom 4 bits of this register are read only and return zeroes when read.

This register must be initialized by the configuration software. For the purpose of address decode,

address bits A19:0 are assumed to be 0. Thus, the bottom of the defined memory address range will

be aligned to a 1-MB boundary.

Bits

Default,

Access

Description

15:4

FFFFh

R/W

Prefetchable Memory Address Base (PMBASE). These bits corresponds to A31:20

of the lower limit of the address range passed by bridge device 1 across AGP.

3:0 Reserved