Hub Datasheet

100 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.7.3 PCICMD1—PCI Command Register (D1:F0)
Address Offset: 04–05h
Default Value: 0000h
Attribute: RO, R/W
Size: 16 bits
Bits
Default,
Access
Description
15:10 Reserved
9
0b
RO
Fast Back-to-Back Enable (FB2B). Hardwired to 0. Not Applicable.
8
0b
R/W
SERR Message Enable (SERRE). This bit is a global enable bit for Device 1 SERR
messaging. The MCH communicates the SERR# condition by sending an SERR
message to the Intel
®
ICH4.
0 = SERR message is not generated by the MCH for Device 1.
1 = MCH is enabled to generate SERR messages over HI for specific Device 1 error
conditions that are individually enabled in the BCTRL1 register. The error status is
reported in the PCISTS1 register.
7
0b
RO
Address/Data Stepping (ADSTEP). Hardwired to 0. Address/data stepping is not
implemented in the MCH.
6
0b
RO
Parity Error Enable (PERRE). Hardwired to 0. Parity checking is not supported on the
primary side of this device.
5 Reserved
4
0b
RO
Memory Write and Invalidate Enable (MWIE). Hardwired to 0. Not implemented.
3
0b
RO
Special Cycle Enable (SCE). Hardwired to 0. Not implemented.
2
0b
R/W
Bus Master Enable (BME).
0 = AGP Master initiated Frame# cycles are ignored by the MCH. The result is a
master abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI
bridge effectively disabled the bus master on the primary side. (Default)
1 = AGP master-initiated Frame# cycles are accepted by the MCH if they hit a valid
address decode range. This bit has no affect on AGP Master originated SBA or
PIPE# cycles.
1
0b
R/W
Memory Access Enable (MAE).
0 = Disable. All of device 1’s memory space is disabled.
1 = Enable. Enables the Memory and Pre-fetchable memory address ranges defined
in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
0
0b
R/W
I/O Access Enable (IOAE).
0 = Disable. All of device 1’s I/O space is disabled.
1 = Enable. Enables the I/O address range defined in the IOBASE1, and IOLIMIT1
registers.