Datasheet

DRAM Controller Registers (D0:F0)
92 Datasheet
1RWC/S0b
Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory
read data transfer had an uncorrectable multiple-bit error. When this bit is set,
the address, channel number, and device number that caused the error are
logged in the register. Once this bit is set, the fields are locked until the
processor clears this bit by writing a 1. Software uses bits [1:0] to detect
whether the logged error address is for Single or Multiple-bit error. This bit is
reset on PWROK.
0RWC/S0b
Single-bit DRAM ECC Error Flag (DSERR): If this bit is set to 1, a memory
read data transfer had a single-bit correctable error and the corrected data was
sent for the access. When this bit is set the address and device number that
caused the error are logged in the DEAP register. Once this bit is set the DEAP,
DERRSYN, and DERRDST fields are locked to further single bit error updates until
the processor clears this bit by writing a 1. A multiple bit error that occurs after
this bit is set will overwrite the DEAP and DERRSYN fields with the multiple-bit
error signature and the DMERR bit will also be set. A single bit error that occurs
after a multi-bit error will set this bit but will not overwrite the other fields. This
bit is reset on PWROK.
Bit Access
Default
Value
Description