Datasheet

Intel Manageability Engine Subsystem PCI (D3:F0,F3)
196 Datasheet
7.1.6 CLS—Cache Line Size
B/D/F/Type: 0/3/0/PCI
Address Offset: Ch
Default Value: 00h
Access: RO
Size: 8 bits
7.1.7 MLT—Master Latency Timer
B/D/F/Type: 0/3/0/PCI
Address Offset: Dh
Default Value: 00h
Access: RO
Size: 8 bits
7.1.8 HTYPE—Header Type
B/D/F/Type: 0/3/0/PCI
Address Offset: Eh
Default Value: 80h
Access: RO
Size: 8 bits
Bit Access
Default
Value
Description
7:0 RO 00h Cache Line Size (CLS): Not implemented, hardwired to 0.
Bit Access
Default
Value
Description
7:0 RO 00h Master Latency Timer (MLT): Not implemented, hardwired to 0.
Bit Access
Default
Value
Description
7RO 1b
Multi-Function Device (MFD): Indicates the HECI host controller is part of a
multi-function device.
6:0 RO 0000000b
Header Layout (HL): Indicates that the HECI host controller uses a target
device layout.