Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH Development Kit User’s Manual April 2007 Order Number: 311274-009
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Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Contents 1.0 About This Manual ..................................................................................................... 7 1.1 Content Overview................................................................................................ 7 1.2 Text Conventions ................................................................................................ 7 1.3 Technical Support...................................................
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 4.1 4.2 4.3 4.4 4.5 Power Button ....................................................................................................37 Sleep States Supported ......................................................................................37 4.2.1 S0 State ................................................................................................37 4.2.2 S1 State ....................................................................
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Back Plate in Place ................................................................................................... 19 Heatsink Mounted on CPU ......................................................................................... 19 Screw Tightening Order ............................................................................................ 20 MCH Heatsink Top View ...............
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Revision History Date Revision Description April 2007 009 Section Section Section Section 2.6.9 updated to clarify that video card is not included in the kit. 2.3 updated to remove the reference to the Blue stand and add the standoffs. 2.6.11 added safety warning. 3 updated with correct part number for CPU heat sink fan. March 2007 008 Updates to Chapter 2.0, “Getting Started” to include safety warnings.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 1.0 About This Manual This manual describes how to set up and use the evaluation board and other components included in your Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH Development Kit. 1.1 Content Overview Chapter 1.0, “About This Manual” – Description of conventions used in this manual and instructions for obtaining literature and contacting customer support. Chapter 2.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH they are collectively called CSn#. A pound symbol (#) appended to a signal name identifies an active-low signal. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P1.0).
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Units of Measure The following abbreviations are used to represent units of measure: 1.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 1.4 Product Literature You can order product literature from the following Intel literature centers. 1.5 U.S. and Canada 1-800-548-4725 U.S. (from overseas) 708-296-9333 Europe (U.K.) 44(0)1793-431155 Germany 44(0)1793-421333 France 44(0)1793-421777 Japan (fax only) 81(0)120-47-88-32 Related Documents Table 1 is a partial list of the available collateral. For the full lists, contact your local Intel representative. Table 1.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 2.0 Getting Started This chapter identifies the Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH Development Kit’s key components, features and specifications. It also describes how to set up the board for operation. Note: This manual assumes you are familiar with basic concepts involved with installing and configuring hardware for a PC or server system. 2.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 2.2 Evaluation Board Features The evaluation board features are summarized below: • CPU — Two Dual-Core Intel Xeon processors LV capable of 667 MHz Front Side Bus — On-board processor voltage regulators compatible with EmVRM11 Design Guide • Intel® E7520 MCH and Intel® 6300ESB ICH — Supports three PCI Express x8 slots — Four DDR2–400 DIMMs on two channels (8 slots total) • System I/O — From 6300ESB 1 PCI 2.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Drivers included: Windows Chipset INF Install Utility version 7.0.0.1019 Optional Intel 6300ESB ICH chipset driver updates Linux Driver Packages RedHat* Enterprise Linux 3.0 Server driver updates Note: Software in the kit is provided free by the vendor and is only licensed for evaluation purposes. Refer to the documentation in your Development Kit for further details on any terms and conditions that may be applicable to the granted licenses.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 1. Board before Installing Additional Hardware 2.6.1 Safety Ensure a safe work environment. Make sure you are in a static-free environment before removing any components from their anti-static packaging. The evaluation board is susceptible to electrostatic discharge, which may cause product failure or unpredictable operation.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Check jumper settings. Verify that the jumpers are set in their default state. Refer to Section 6.4 for detailed descriptions of all jumpers and their default settings indicated in bold. 2.6.3 Installed Hardware Verify installed hardware.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 2. Location for the CPU and MCH for Heatsink Installation Caution: Applying excess pressure may cause damage to the CPU. Note: Do not turn power on until the CPU thermal solution has been installed. 2.6.5 CPU Heatsink Installation This section details how to install the CPU heatsink. This section may not apply if the CPU heatsink is pre-installed on the board.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 3. CPU Heatsink Top and Bottom View 1. Make certain that the processor is firmly seated in the socket, and the package is secured using a flathead screwdriver. Note: This shows CPU1 populated. However for single CPU operation socket 0 should be populated. Figure 4.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 2. Clean the top surface of the processor die with a clean towel and isopropyl alcohol (IPA). Figure 5.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 3. Install the back plate to the bottom side of the PCB at the CPU location. Align the standoffs to the four mounting holes in the board. Note: There is a non-electrically conductive tape to hold the back plate in place until the heatsink is completely installed. Figure 6. Back Plate in Place 4. Mount the heatsink to the CPU. Ensure the TIM and die have contact. Figure 7.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 5. Align the screws (4x at corners) to the threaded holes of the standoffs on the back plate. Using the Phillips head screwdriver, tighten the four screws in a diagonal manner (as shown in the diagram). Tighten each screw half of the screw length for A to B and follow by ¼ for C to D. Then tighten A to B until the screw hard stops and repeat for C to D. The screws are designed to compress the springs a predetermined amount. Figure 8.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 1. Clean the top surface of the MCH die with a clean towel and isopropyl alcohol (IPA). Figure 10. Clean Top of MCH Die 2. Hook one end of the heatsink clip to one of the anchors located near the corner of the MCH. Securely hold the other end of the heatsink clip. Figure 11.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 3. Hold the clip firmly to the anchor to prevent the heatsink from moving. Attach the other end of the clip to the other anchor. Ensure that the heatsink is level with the MCH package. Figure 12. Hook Heatsink Clip to Second Anchor 4. Plug the fan connector to the fan pin header on the board. Note: The heatsink removal process is the reverse of the installation procedure. 2.6.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH configuration you choose.) A CD-ROM drive or additional hard drive may be installed as a primary slave device. Follow this procedure to install a hard drive on the evaluation board: 1. Verify that the jumper on the hard drive is set correctly for single or master, depending on your configuration. 2. Install the hard drive. This can be done using either the IDE or SATA. IDE Installation: Note: a.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 2.6.10 Connect the Keyboard and Mouse Connect a PS/2 mouse and keyboard to the stacked PS/2 connector on the evaluation board. The bottom connector, often purple, is the keyboard connector and the top, often green, is the mouse connector. Alternatively, you may plug a USB keyboard and a USB mouse into the USB connectors on the evaluation board. Note: Keyboard and mouse are not included in this Development Kit. 2.6.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 3.0 Theory of Operation 3.1 Block Diagram Figure 13. Block Diagram of Layout Dual-Core ® ® Intel Xeon processor LV Dual-Core ® Intel Xeon® processor LV 167 MHz/667 MT/s X8 PCIe C X8 PCIe B X8 PCIe Intel® E7520 DDR2 400 Single or dual channel support (MCH) }A HL 1.5 Interface Two SATA Four USB (2.0) Ports PCI-X 66 MHz Intel® 6300ESB R R PCI 32/33 Two IDE LPC Bus SIO TPM R VGA FWH 3.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 3.3 System Features Processor • Supports two Dual-Core Intel Xeon processors LV • On-board processor voltage regulators compatible with EmVRD11 Design Guide.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 3.3.1 Dual-Core Intel® Xeon® processor LV • 667 MHz FSB 3.3.2 Intel® E7520 MCH and Intel® 6300ESB ICH Chipset The features of the chipsets are detailed below. 3.3.2.1 Intel® E7520 MCH Memory Controller Hub (MCH) The architecture of the MCH provides the performance and feature set required for dual processor-based volume to performance servers.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 3.3.3 Memory Subsystem The memory subsystem is designed to support Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) using the Intel® E7520 MCH. The MCH provides two independent DDR channels, which support DDR2-400 DIMMs. The peak bandwidth of each DDR2 branch channel is 3.2 GByte/s (8 bytes x 400 MT/s) with DDR2-400.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 14. DDR2-400 Memory—DIMM Ordering 3.3.6 Intel® 82802AC Firmware Hub (FWH) A socketed FLASH device is used to store system BIOS as well as an Intel® Random Number Generator (RNG). A bootblock locking jumper is provided to allow a mechanical means of protecting the bootblock BIOS firmware. All BIOS programming is controlled via software.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 15. ITP location 3.3.9 Power Diagram Figure 16 shows the power distribution for the CRB. Refer to the CRB schematics for details on the power distribution logic (contact your Intel field sales representative to obtain the schematics).
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 16. Power Distribution Block Diagram DDR DIMMS 1.8 V 50 A 12 V 18A DDR S3 S3_ CNTRL Switch -12 V VCCP 0 VCCP 1 1A 0.8375 - 1.6000 V 50 A 0.8375 - 1.6000 V 50 A VRM 11 5. 0V 50A 1. 5 V 13 A VCCP 1.05 V 6.0 A -5 . 0V 0.5 A 1 .8VDDRSB 3A 5 . 0VSTBY 2.5 A 3. 3V 3 . 3VSTBY 1. 5VSTBY 3.0 A 0.8 A 3 .3 AUX 28A 1.7 A 450 W ATX 3.3.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 17. Clock Block Diagram CPU0_BCLK CPU0 CPU1_BCLK CPU1 ITP_BCLK ITP DDRA_CMDCLK[0..3] DDRA DDRB_CMDCLK[0.3] DDRB MCH_BCLK MCH_66MHZ_CLK MCH SMA LPC_14MHZ_CLK ICH_33MHZ_CLK ICH_PX_PCLK0[0..1] PCI-X ICH ICH_HI66MHZ_CLK 14.318 MHz LPC_14MHZ_CLK SIO ICH_SUSCLK 32.786 kHz SIO_33MHZ_CLK ICH_SRC_100MHZ_CLK ICH_PX66MHZ_CLK MCH_SRC_100MHZ_CLK ICH_USB_48MHZ_CLK MIDBUS_100MHZ_CLK PCI Express Midbus Probe 29.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 18. Platform Reset Diagram FWH TPM PCI 32 PCIRST2# VGA IDERST# IDE SIO Port 80 PCIRST1# PCI-X LPC Debug SYS_RESET# PCIRST_N PCI-X ICH CPU 0 CPURST# MCH CPU 1 VRM_PWRGD ITP SYS_PWRGD_3V3 3.3.12 PCI-E PCI-E PCI-E Slots SMBus Figure 19 below illustrates the routing of the SMBus signal among the components.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH SMBus Block Diagram Allagash SMBus 3.3VSBY 3.3VSBY ICH_SMB ICH-S SMBus Repeater ITP XDP SMBus Repeater TPM SMBus Repeater ID EEPROM 3.3V 3.3V PCI Express Slot (Slot # 3) PCI Express Slot (Slot # 4) 0-ohm SMBus Repeater MCH_SMB Intel® E7520PF DB800 3.3.13 0-ohm 0-ohm SMBus Master Only CK409B HECETA 7 SMBALERT_N Figure 19.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH PCI-E 8x MSI PCI-E PCI-E 8x MSI PCI-E PCI-E 8x MSI PCI-E IRQ Routing Diagram MSI MSI MSI MSI PCI-E HI MCH PCI Slot REQ/GNT: 0 IDSEL: AD16 A B C D MSI FSB SMI NMI FSB SMI CPU0 NMI MSI Figure 20.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH override enable, jumper controls whether or not the VID header jumpers control the VID to the regulator or not. 1 Table 5. 3.4 Processor VRD Settings VR6 VR5 VR4 VR3 VR2 VR1 Vccmax VR6 VR5 VR4 VR3 VR2 VR1 Vccmax 0 0 0 0 0 1 1.60000 1 0 0 0 1 0 1.18750 0 0 0 0 1 0 1.58750 1 0 0 0 1 1 1.17500 0 0 0 0 1 1 1.57500 1 0 0 1 0 0 1.16250 0 0 0 1 0 0 1.56250 1 0 0 1 0 1 1.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 4.0 Platform Management The following sections describe how the system power management operates, and how the different ACPI states are implemented. Platform management involves: • ACPI implementation-specific details • System monitoring, control, and response to thermal, voltage, and intrusion events • BIOS security 4.1 Power Button The system power button is connected to the I/O controller component.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Power must be switched from the normal 1.8 V rail to standby 1.8 V, because the ATX 12v 450 W power supply does not directly supply a standby 1.8 V rail. The sequence to enter Suspend to RAM is as follows: 1. The OS and BIOS prepare for S3 sleep state. 2. The OS sets the appropriate sleep bits in the I/O controller. 3. The I/O controller drives STPCLK to the processors. 4.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 4.2.10 Wake from S5 State The power button is used to wake from S5. 4.3 PCI PM Support This design holds the system reset signal low when in a sleep state. The system supports the PCI PME# signal and provides 3.3 V standby to the PCI and PCI Express slots. This support allows any compliant PCI or PCI Express card to wake up the system from any sleep state except mechanical off. Because of the limited amount of power available on 3.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 5.0 Driver and OS Support The CRB supports the following operating systems: • Red Hat* EL 3.0 AS and WS • QNX Neutrino* • Windows* Server 2003 • Microsoft* Windows XP and embedded XP Note: Operating systems are not included in the Development Kit.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.0 Hardware Reference This section provides reference information on the hardware, including locations of evaluation board components, connector pinout information, and jumper settings. Figure 21 shows the evaluation board. Figure 21.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.1 Chipset Components Table 6 lists the chipset and other major components on the evaluation board. Table 6. Chipset Components Component Designator 6.2 Component Description ® U5E1 Intel U3F1 Intel® 6300ESB I/O Controller Hub (ICH) U1H1 Intel® 82802AC Firmware Hub (FWH) E7520 Memory Controller Hub (MCH) Expansion Slots and Sockets Table 7 lists the expansion slots and sockets on the evaluation board. Table 7.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Table 8.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.2.2 32-Bit PCI Connector Table 9 presents the signals assigned to the 32-bit PCI slot connector found at J2B1. Table 9.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Table 9. 32-Bit 5 V PCI Connector Pinout (Sheet 2 of 2) Pin 6.2.3 Signal Pin Signal A38 STOP# B38 GND A39 3.3 V B39 LOCK# A40 SDONE B40 PERR# A41 SBO# B41 3.3 V A42 GND B42 SERR# A43 PAR B43 3.3 V A44 AD15 B44 C/BE1# A45 3.3 V B45 AD14 A46 AD13 B46 GND A47 AD11 B47 AD12 A48 GND B48 AD10 A49 AD9 B49 GND A50 KEY B50 KEY A51 KEY B51 KEY A52 CBEO# B52 AD8 A53 3.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Table 10. PCI-X Connector Pinout (Sheet 2 of 4) Pin Signal Pin Signal A10 3.3 V B10 Reserved A11 Reserved B11 PRSNT2# A12 KEY B12 KEY A13 KEY B13 KEY A14 3.3 VAUX B14 Reserved A15 RST# B15 GND A16 3.3 V B16 CLK A17 GNT# B17 GND A18 GND B18 REQ# A19 PME# B19 3.3 V A20 AD30 B20 AD31 A21 3.3 V B21 AD29 A22 AD28 B22 GND A23 AD26 B23 AD27 A24 GND B24 AD25 A25 AD24 B25 3.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Table 10. PCI-X Connector Pinout (Sheet 3 of 4) Pin Signal Pin Signal A50 GND B50 GND A51 GND B51 GND A52 CBEO# B52 AD8 A53 3.3 V B53 AD7 A54 AD6 B54 3.3 V A55 AD4 B55 AD5 A56 GND B56 AD3 A57 AD2 B57 GND A58 AD0 B58 AD1 A59 3.3 V B59 3.3 V A60 REQ64# B60 ACK64# A61 5V B61 5V A62 5V B62 5V A63 GND B63 Reserved A64 C/BE7# B64 GND A65 C/BE5# B65 C/BE6# A66 3.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Table 10. PCI-X Connector Pinout (Sheet 4 of 4) Pin 6.2.4 Signal Pin Signal A90 GND B90 AD33 A91 AD32 B91 GND A92 Reserved B92 Reserved A93 GND B93 Reserved A94 Reserved B94 GND Processor Sockets The processor is keyed so that it fits into the socket in one particular orientation. 6.2.5 Firmware Hub (FWH) BIOS Socket The system boot ROM is installed on the Intel® 82802AC Firmware Hub.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.3.1 SATA Connector Table 12. SATA Connector Pinout Pin 6.3.2 Connector Description 1 GND 2 A+ 3 A- 4 GND 5 B- 6 B+ 7 GND IDE Connector The evaluation board has a 40-pin connector for the IDE controller present in the Intel® 6300ESB ICH. Table 13 lists the signals assigned to the IDE connector. Table 13.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.3.3 Floppy Drive Connector The evaluation board provides one 34-pin floppy connector, which is located at J1K1. Table 14. Floppy Drive Connector Pinout Pin 6.3.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.4 Jumpers The evaluation board has a number of jumpers that control various functions of the system. Table 16 presents the descriptions of the jumpers and their settings. Figure 22 illustrates the locations of the jumpers on the board. Table 16.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Figure 22.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.5 SMBUS Headers The SMBUS headers are used to connect the SMBUS. Refer to the following tables for pinout information. Table 17 describes the SMBUS 3.3 V STBY pinout. Table 17. SMBUS 3.3 V STBY Pinout Pin 6.6 Connector Description 1 SMBDAT 2 GND 3 SMB CLK Back Panel Connectors The evaluation board contains a number of connectors for external system devices and peripherals. Figure 23 shows the peripheral connectors.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH Table 19. Parallel Port Connector Pinout Pin 6.6.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 6.6.5 Video Port Note: This section may not apply if video connector is not present on the board. Table 22 lists the signals assigned to the video port connector. Table 22.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 7.0 Board Setup Checklist The following is a checklist of items to ensure proper functionality of the CRB. • All cables are properly plugged in: — Hard drives — SATA and/or IDE — Monitor, keyboard, mouse — Additional peripherals such as CD, DVD, floppy, etc. — Power • Fans are securely in place and plugged into the appropriate jumpers. • Memory, PCI, and PCI Express cards are secured in slots. • RTC battery is installed.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 8.0 Debug Procedure The debug procedure in this section is used to determine baseline functionality for the Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH Development Kit. This is a cursory set of tests designed to provide a level of confidence in the platform operation. 8.1 Level 1 Debug (Port80/BIOS) Refer to the steps in Table 23 when debugging a board that does not boot. Table 23.
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH 8.3 Level 3 Debug (Voltage References) Table 25 includes the first items to look at when debugging a board that is not booting. Table 25. Level 3 Debug (Voltage Reference) Step Test Pass/Fail Criteria Cause of Failure 1 MCH DDR2 Channel A Vref 0.9 V Vref incorrect: check resistor values 2 MCH DDR2 Channel B Vref 0.9 V Vref incorrect: check resistor values 3 MCH Hublink Vref 0.
