Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 187
Datasheet Volume One, February 2014
PIROM
Bits are set when a feature is present, and cleared when they are not.
9.3.8.4 MPSUP: Multiprocessor Support
This location contains 2 bits for representing the supported number of physical
processors on the bus. These two bits are LSB aligned where 00b equates to non-
scalable 2 socket (2S) operation, 01b to scalable 2 socket (S2S), 10 to scalable 4
socket (S4S), and scalable 8 socket (S8S). The Intel® Xeon® E7 v2 processor is a
S2S, S4S, or S8S processor. The first six bits in this field are reserved for future use.
Writes to this register have no effect.
Example: A scalable 8 socket processor will have a value of 03h at offset 71h.
9.3.8.5 TCDC: Tap Chain Device Count
At offset 73, a 4-bit hex digit is used to tell how many devices are in the TAP Chain.
Because the Intel® Xeon® E7 v2 processor has ten cores, this field would be set to Ah.
9.3.8.6 RES9: Reserved 9
This location is reserved. Writes to this register have no effect.
Offset: 72h
Bit Description
7:2 RESERVED
000000b-111111b: Reserved
1:0 Multiprocessor Support
2S, S2S, S4S or S8S indicator
00b: Non-Scalable 2 Socket
01b: Scalable 2 Socket
10b: Scalable 4 Socket
11b: Scalable 8 Socket
Offset: 73h
Bit Description
7:0 TAP Chain Device Count
0000h-FFFFh: Reserved
Offset: 74h-75h
Bit Description
15:0 RESERVED
0000h-FFFFh: Reserved