Specification Update

Summary Table of Changes
Intel
®
Xeon
®
Processor E7 v2 Product Family 11
Specification Update January 2015
CF84 XNo FixRDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result
CF85 XNo FixMONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
CF86 XNo Fix
PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate
With 32-bit Length Registers
CF87 XNo FixClock Modulation Duty Cycle Cannot Be Programmed to 6.25%
CF88 XNo FixProcessor May Livelock During On Demand Clock Modulation
CF89 XNo FixPerformance Monitor Counters May Produce Incorrect Results
CF90 XNo Fix
Virtual-APIC Page Accesses with 32-Bit PAE Paging May Cause a System
Crash
CF91 XNo FixIA32_FEATURE_CONTROL MSR May be Un-Initialized on a Cold Reset
CF92 XNo FixPEBS May Unexpectedly Signal a PMI After the PEBS Buffer is Full
CF93 XNo FixExecution of GETSEC[SEXIT] May Cause a Debug Exception to Be Lost
CF94 XNo Fix
An Uncorrectable Error Logged in IA32_MC2_STATUS May also Result in a
System Hang
CF95 XNo Fix
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not
Updated After a UC Error is Logged
CF96 XNo Fix
IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report the Highest
Index Value Used for VMCS Encoding
CF97 XNo FixThe Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging
CF98 XNo FixEPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly
CF99 XNo Fix
Intel® QuickData Technology DMA Access to Invalid Memory Address May
Cause System Hang
CF100 XNo FixCPUID Faulting is Not Enumerated Properly
CF101 XNo FixTSC is Not Affected by Warm Reset
CF102 XNo FixPECI_WAKE_MODE is Always Reported as Disabled
CF103 XNo FixPoisoned PCIe* AtomicOp Completions May Return an Incorrect Byte Count
CF104 XNo Fix
Incorrect Speed and De-emphasis Level Selection During DMI Compliance
Testing
CF105 XNo Fix
PCIe* Device 3 Does Not Log an Error in UNCERRSTS When an Invalid
Sequence Number in an Ack DLLP is Received
CF106 XNo FixProgrammable Ratio Limits For Turbo Mode is Reported as Disabled
CF107 XNo FixPCIe* TLPs in Disabled VC Are Not Reported as Malformed
CF108 XNo FixPCIe* Link May Fail to Train to 8.0 GT/s
CF109 XNo FixPCIe* Header of a Malformed TLP is Logged Incorrectly
CF110 XNo Fix
PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0
During Upconfiguration
CF111 XNo Fix
Single PCIe* ACS Violation or UR Response May Result in Multiple
Correctable Errors Logged
CF112 XNo FixPCIe* Extended Tag Field May be Improperly Set
CF113 XNo FixPower Meter May Under-Estimate Package Power
CF114 XNo FixDTS2.0 May Report Inaccurate Temperature Margin
CF115 XNo FixA DMI UR May Unexpectedly Cause a CATERR# After a Warm Reset
CF116 XNo FixPECI May Not be Able to Access IIO CSRs
Table 1. Summary Table of Changes (Sheet 4 of 6)
No.
Stepping
Status Errata
D1