Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 87
Register Description
3.6.15 HIA_NERR—HI_A Next Error Register (D0:F1)
Address Offset: 52h
Default Value: 00h
Sticky Yes
Attribute: RO, R/WC
Size: 8 bits
The first HI_A error will be stored in the HIA_FERR Register. This register stores all future HI_A
errors. Multiple bits in this register may be set.
Note: Software must write a 1 to clear bits that are set.
3.6.16 SCICMD_HIA—SCI Command Register (D0:F1)
Address Offset: 58h
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determines whether SCI will be generated when the associated flag is set in the
HIA_FERR or HIA_NERR Register. When an error flag is set in the HIA_FERR or HIA_NERR
Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or
SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
Description
7 Reserved
6
0b
R/WC
HI_A Target Abort.
0 = No Target Abort on MCH originated HI_A cycle terminated.
1 = MCH originated HI_A cycle was terminated with a Target Abort.
5 Reserved
4
0b
R/WC
HI_A Data Parity Error Detected.
0 = No data parity error detected.
1 = Parity error on a HI_A data transfer.
3:1 Reserved
0
0b
R/WC
HI_A Data Address/Command Error Detected.
0 = No address or command parity error detected.
1 = Parity error on a HI_A address or command.
Bits
Default,
Access
Description
7 Reserved
6
0b
R/W
SCI on HI_A Target Abort Enable.
0 = No SCI generation
1 = Generate SCI if bit 6 is set in HIA_FERR or HIA_NERR
5 Reserved
4
0b
R/W
SCI on HI_A Data Parity Error Detected Enable.
0 = No SCI generation
1 = Generate SCI if bit 4 is set in HIA_FERR or HIA_NERR
3:1 Reserved
0
0b
R/W
SCI on HI_A Data Address/Comment Error Detected Enable.
0 = No SCI generation
1 = Generate SCI if bit 0 is set in HIA_FERR or HIA_NERR