Hub Datasheet
Intel
®
E7505 Chipset MCH Datasheet 61
Register Description
3.5.19 DRT—DRAM Timing Register (D0:F0)
Address Offset: 78–7Bh
Default Value: 0000 0010h
Attribute: RO, R/W
Size: 32 bits
This register controls the timing of the DRAM Controller.
Bits
Default,
Access
Description
31:30 Reserved
29
0b
R/W
Back To Back Write-Read Turn Around. This field determines the minimum number of
CMDCLK (command clocks, at 100 MHz) between Write-Read commands. It applies to
WR-RD pairs to different rows. A WR-RD pair to the same row has sufficient turnaround
due to the tWTR timing parameter. The purpose of this bit is to control the turnaround
time on the DQ bus.
0 = 3 clocks between WR-RD commands (2 turnaround clocks on DQ)
1 = 2 clock between WR-RD commands (1 turnaround clock on DQ)
NOTE: The bigger turn-around is used in large configurations where the difference in
total channel delay between the fastest and slowest DIMM is large.
28
0b
R/W
Back To Back Read-Write Turn Around. This field, along with bit 15 of the REROTC
register (offset 80–81h), determines the minimum number of CMDCLK (command
clocks, at 100/133 MHz) between Read-Write commands. It applies to RD-WR pairs to
any destination (in same or different rows). The purpose of this bit is to control the
turnaround time on the DQ bus.
NOTES:
1. Number in parenthesis is for single channel operation.
2. The bigger turn-around is used in large configurations where the difference in total
channel delay between the fastest and slowest DIMM is large.
27
0b
R/W
Back To Back Read Turn Around. This field determines the minimum number of
CMDCLK (command clocks, at 100 MHz) between two Reads to different rows. The
purpose of this bit is to control the turnaround time on the DQ bus.
0 = 4 clocks between RD commands to different rows (2 turnaround clocks on DQ)
1 = 3 clocks between RD commands to different rows (1 turnaround clock on DQ)
NOTE: The bigger turn-around is used in large configurations where the difference in
total channel delay between the fastest and slowest DIMM is large.
DRT
bit 28
REROTC
bit 15
Description
0 1 6 (8) clocks between RD-WR commands
0 0 5 (7) clocks between RD-WR commands
1 1 5 (7) clocks between RD-WR commands
1 0 4 (6) clocks between RD-WR commands