Hub Datasheet

6 Intel
®
E7505 Chipset MCH Datasheet
3.8.7 BCC2—Base Class Code Register (D2:F0)......................................... 126
3.8.8 MLT2—Master Latency Timer (Scratch Pad) Register (D2:F0) ........... 127
3.8.9 HDR2—Header Type Register (D2:F0)................................................ 127
3.8.10 PBUSN2—Primary Bus Number Register (D2:F0) .............................. 127
3.8.11 SBUSN2—Secondary Bus Number Register (D2:F0).......................... 128
3.8.12 SUBUSN2—Subordinate Bus Number Register (D2:F0)..................... 128
3.8.13 IOBASE2—I/O Base Address Register (D2:F0)................................... 129
3.8.14 IOLIMIT2—I/O Limit Address Register (D2:F0).................................... 129
3.8.15 SEC_STS2—Secondary Status Register (D2:F0) ............................... 130
3.8.16 MBASE2—Memory Base Address Register (D2:F0) ........................... 131
3.8.17 MLIMIT2—Memory Limit Address Register (D2:F0) ............................ 131
3.8.18 PMBASE2—Prefetchable Memory Base Address Register (D2:F0).... 132
3.8.19 PMLIMIT2—Prefetchable Memory Limit Address Register (D2:F0)..... 132
3.8.20 BCTRL2—Bridge Control Register (D2:F0) ......................................... 133
3.9 Hub Interface_B PCI-to-PCI Bridge Error Reporting Registers (Device 2, Function
1)134
3.9.1 VID—Vendor Identification Register (D2:F1) ....................................... 135
3.9.2 DID—Device Identification Register (D2:F1)........................................ 135
3.9.3 PCICMD—PCI Command Register (D2:F1) ........................................ 136
3.9.4 PCISTS—PCI Status Register (D2:F1) ................................................ 136
3.9.5 RID—Revision Identification Register (D2:F1) ..................................... 137
3.9.6 SUBC—Sub-Class Code Register (D2:F1) .......................................... 137
3.9.7 BCC—Base Class Code Register (D2:F1)........................................... 137
3.9.8 HDR—Header Type Register (D2:F1).................................................. 138
3.9.9 SVID—Subsystem Vendor Identification Register (D2:F1) .................. 138
3.9.10 SID—Subsystem Identification Register (D2:F1) ................................. 138
3.9.11 HIB_FERR—HI_B First Error Register (D2:F1) ................................... 139
3.9.12 HIB_NERR—HI_B Next Error Register (D2:F1)................................... 140
3.9.13 SERRCMD2—SERR Command Register (D2:F1) .............................. 141
3.9.14 SMICMD2—SMI Command Register (D2:F1)...................................... 142
3.9.15 SCICMD2—SCI Command Register (D2:F1) ...................................... 143
4 System Address Map............................................................................................ 145
4.1 System Memory Spaces ................................................................................... 145
4.1.1 VGA and MDA Memory Spaces........................................................... 148
4.1.2 PAM Memory Spaces .......................................................................... 149
4.1.3 I/O APIC Memory Space...................................................................... 150
4.1.4 System Bus Interrupt Memory Space................................................... 150
4.1.5 High SMM Memory Space ................................................................... 150
4.1.6 AGP Aperture Space (Device 0 and Device 1 BAR)............................ 150
4.1.6.1 AGP DRAM Graphics Aperture ............................................... 151
4.1.7 Device 2 Memory and Prefetchable Memory ....................................... 151
4.1.8 HI_A Subtractive Decode..................................................................... 151
4.2 I/O Address Space ............................................................................................ 151
4.3 SMM Space....................................................................................................... 152
4.3.1 System Management Mode (SMM) Memory Range ............................ 152
4.3.2 TSEG SMM Memory Space................................................................. 152
4.3.3 High SMM Memory Space ................................................................... 153
4.3.4 SMM Space Restrictions...................................................................... 153
4.3.5 SMM Space Definition.......................................................................... 153