Hub Datasheet

50 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.8 MLT—Master Latency Timer Register (D0:F0)
Address Offset: 0Dh
Default Value: 00h
Attribute: RO
Size: 8 bits
Device 0 in the MCH is not a PCI master; therefore, this register is not implemented.
3.5.9 HDR—Header Type Register (D0:F0)
Address Offset: 0Eh
Default Value: 00h or 80h
Attribute: RO
Size: 8 bits
Bits
Default,
Access
Description
7:0 Reserved
Bits
Default,
Access
Description
7:0
00h or
80,
RO
PCI Header (HDR). This read only field indicates whether the MCH is a multi-function
device.
00h = Single Function Device (Function 1 is disabled in address offset E0h, bit 0)
80h = Multi Function Device (Function 1 is enabled in address offset E0h, bit 0)