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Intel
®
E7505 Chipset MCH Datasheet 47
Register Description
3.5.3 PCICMD—PCI Command Register (D0:F0)
Address Offset: 04–05h
Default Value: 0006h
Attribute: RO, R/W
Size: 16 bits
Since MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented.
Bits
Default,
Access
Description
15:10 Reserved
9
0b
RO
Fast Back-to-Back Enable (FB2B). Hardwired to 0. This bit controls whether or not the
master can do fast back-to-back write. Since device 0 is strictly a target, this bit is not
implemented.
8
0b
R/W
SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR messaging.
The MCH does not have an SERR signal. The MCH communicates the SERR condition
by sending an SERR message over HI_A to the Intel
®
ICH4.
0 = Disable. SERR message is not generated by the MCH for Device 0.
1 = Enable. MCH is enabled to generate SERR messages over HI_A for specific
Device 0 error conditions that are individually enabled in the ERRCMD register. The
error status is reported in the ERRSTAT and PCISTS registers.
NOTE: Note that this bit only controls SERR messaging for the Device 0. Devices 1-6
have their own SERR bits to control error reporting for error conditions
occurring on their respective devices. The control bits are used in a logical OR
manner to enable the SERR HI message mechanism.
7
0b
RO
Address/Data Stepping Enable (ADSTEP). Hardwired to 0. Address/data stepping is
not implemented in the MCH.
6
0b
R/W
Parity Error Enable (PERRE).
0 = Disable. MCH does not take any action when it detects a parity error on HI_A.
1 = Enable. MCH generates an SERR message over HI_A to the ICH4 when an
address or data parity error is detected by the MCH on HI_A (DPE set in PCISTS)
and SERRE is set to 1.
5
0b
RO
VGA Palette Snoop Enable (VGASNOOP). Hardwired to 0. The MCH does not
implement this bit.
4
0b
RO
Memory Write and Invalidate Enable (MWIE). Hardwired to 0. The MCH never issues
memory write and invalidate commands.
3
0b
RO
Special Cycle Enable (SCE). Hardwired to 0. The MCH does not implement this bit.
2
1b
RO
Bus Master Enable (BME). Hardwired to 1. The MCH is always enabled as a master on
HI_A.
1
1b
RO
Memory Access Enable (MAE). Hardwired to 1. The MCH always allows access to
main memory.
0
0b
RO
I/O Access Enable (IOAE). Hardwired to 0. This bit is not implemented in the MCH.