Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 43
Register Description
3.3.4 AGP Bus Configuration Mechanism
From the chipset configuration perspective, AGP is seen as a PCI bus interface residing on a
Secondary Bus side of the virtual PCI-to-PCI bridges referred to as the MCH Host-to-AGP bridge.
On the Primary bus side, the virtual PCI-to-PCI bridge is attached to PCI Bus #0. Therefore, the
Primary Bus Number register is hardwired to 0. The virtual PCI-to-PCI bridge entity converts Type
#1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the
AGP interface. Type 1 configuration cycles on PCI Bus #0 that have a Bus Number that matches
the Secondary Bus Number of the MCH’s virtual Host-to-AGP bridge will be translated into Type
0 configuration cycles on the AGP interface. The MCH will decode the Device Number field 15:11
and assert the appropriate GAD signal as an IDSEL in accordance with the PCI-to-PCI Bridge
Type 0 configuration mechanism.
If the Bus Number is non-zero, greater than the value programmed into the Secondary Bus Number
register, and less than or equal to the value programmed into the Subordinate Bus Number register
the configuration cycle is targeting a PCI bus downstream of the targeted interface. The MCH will
generate a Type 1 PCI configuration cycle on AGP.
3.4 I/O Mapped Registers
The MCH contains two registers that reside in the processor I/O address space; the Configuration
Address (CONFIG_ADDRESS) register and the Configuration Data (CONFIG_DATA) register.
The Configuration Address register enables/disables the configuration space and determines what
portion of configuration space is visible through the Configuration Data window.