Specification Update

20 Intel

E7320 Memory Controller Hub (MCH) Specification Update

Specification Clarifications

1. Clarification to Section 4.4.1, “Memory Remapping”, in the EDS

Section 4.4.1 currently reads as follows:

4.4.1 Memory Remapping

An incoming address (referred to as a logical address) is checked to see if it falls in the

memory remap window. The bottom of the remap window is defined by the value in the

REMAPBASE register. The top of the remap window is defined by the value in the

REMAPLIMIT register. An address that falls within this window is remapped to the physical

memory starting at the address defined by the TOLM register.

A clarification will be made to Section 4.4.1 by adding a second paragraph which will read as

follows:

4.4.1 Memory Remapping

An incoming address (referred to as a logical address) is checked to see if it falls in the

memory remap window. The bottom of the remap window is defined by the value in the

REMAPBASE register. The top of the remap window is defined by the value in the

REMAPLIMIT register. An address that falls within this window is remapped to the physical

memory starting at the address defined by the TOLM register.

The remap operation increases the latency of CPU to memory accesses (within the remap

area) by three clocks when the pipeline between the CPU interface and memory is empty (the

“idle latency” case). This may result in a measurable performance degradation within the

remap range for latency-sensitive benchmarks that are run on lightly loaded systems. This

latency difference disappears when latency-sensitive benchmarks are run on moderately to

heavily loaded systems.