Datasheet

Signal Description
32 Datasheet
2.4 Controller Link Interface Signals
2.5 Clocks, Reset, and Miscellaneous
EXP_COMPI
I
A
Primary PCI Express Input Current Compensation
EXP2_COMPO
(3210 MCH only)
I
A
Secondary PCI Express Output Current Compensation
This signal is a No Connect for the 3200 MCH.
EXP2_COMPI
(3210 MCH only)
I
A
Secondary PCI Express Input Current Compensation
This signal is a No Connect for the 3200 MCH.
Signal Name Type Description
CL_DATA
I/O
CMOS
Controller Link Data (Bi-directional)
CL_CLK
I/O
CMOS
Controller Link Clock (Bi-directional)
CL_VREF
I
CMOS
Controller Link VREF
CL_RST#
I
CMOS
Controller Link Reset (Active low)
Signal Name Type Description
HPL_CLKINP
HPL_CLKINN
I
CMOS
Differential Host Clock In: These pins receive a differential
host clock from the external clock synthesizer. This clock is used
by all of the MCH logic that is in the Host clock domain.
EXP_CLKINP
EXP_CLKINN
I
CMOS
Differential Primary PCI Express Clock In: These pins
receive a differential 100 MHZ Serial Reference clock from the
external clock synthesizer. This clock is used to generate the
clocks necessary for the support of Primary PCI Express and
DMI.
EXP2_CLKINP
EXP2_CLKINN
(3210 MCH only)
I
CMOS
Differential Secondary PCI Express Clock In: These pins
receive a differential 100 MHZ Serial Reference clock from the
external clock synthesizer. This clock is used to generate the
clocks necessary for the support of Secondary PCI Express.
Note: For the 3200 MCH, this signal pair is not used since only
one 8-lane (x8) PCI Express port is supported.
RSTINB
I
SSTL
Reset In: When asserted this signal will asynchronously reset
the MCH logic. This signal is connected to the PCIRST# output
of the ICH. All PCI Express output signals and DMI output
signals will also tri-state compliant to PCI Express Rev 1.1
specification.
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3 V tolerant.
Signal Name Type Description