Datasheet

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
224 Datasheet
8.15 MBASE1—Memory Base Address
B/D/F/Type: 0/6/0/PCI
Address Offset: 20–21h
Default Value: FFF0h
Access: RW, RO
Size: 16 bits
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary.
Bit Access
Default
Value
Description
15:4 RW FFFh
Memory Address Base (MBASE): Corresponds to A[31:20] of the lower limit
of the memory range that will be passed to PCI Express.
3:0 RO 0h Reserved