Datasheet

Host-Primary PCI Express* Bridge Registers (D1:F0)
164 Datasheet
6.22 INTRLINE1—Interrupt Line
B/D/F/Type: 0/1/0/PCI
Address Offset: 3Ch
Default Value: 00h
Access: RW
Size: 8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
6.23 INTRPIN1—Interrupt Pin
B/D/F/Type: 0/1/0/PCI
Address Offset: 3Dh
Default Value: 01h
Access: RO
Size: 8 bits
This register specifies which interrupt pin this device uses.
6.24 BCTRL1—Bridge Control
B/D/F/Type: 0/1/0/PCI
Address Offset: 3E–3Fh
Default Value: 0000h
Access: RO, RW
Size: 16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface as well as
some bits that affect the overall behavior of the "virtual" Host-PCI Express bridge
embedded within MCH.
Bit Access
Default
Value
Description
7:0 RW 00h
Interrupt Connection (INTCON): This field is used to communicate interrupt
line routing information.
Bit Access
Default
Value
Description
7:0 RO 01h
Interrupt Pin (INTPIN): As a single function device, the PCI Express device
specifies INTA as its interrupt pin. 01h=INTA.
Bit Access
Default
Value
Description
15:12 RO 0h Reserved
11 RO 0b
Discard Timer SERR# Enable (DTSERRE): Not Applicable or Implemented.
Hardwired to 0.
10 RO 0b
Discard Timer Status (DTSTS): Not Applicable or Implemented. Hardwired to
0.