Specification Update

Intel
®
Xeon
®
Processor 7000 Series 29
Specification Update, March 2010
A38. With trap flag (TF) asserted, FP instruction that triggers an unmasked
FP exception may take single step trap before retirement of
instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is
possible for external events to occur, including a transition to a lower power state.
When resuming from the lower power state, it may be possible to take the single step
trap before the execution of the original FP instruction completes.
Implication: A Single Step trap will be taken when not expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A39. Branch trace store (BTS) and precise event based sampling (PEBS)
may update memory outside the BTS/PEBS buffer
Problem: If the BTS/PEBS buffer is defined such that:
• The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum is
not an integer multiple of the corresponding record sizes
• BTS/PEBS absolute maximum is less than a record size from the end of the virtual
address space
• The record that would cross BTS/PEBS absolute maximum will also continue past
the end of the virtual address space
A BTS/PEBS record can be written that will wrap at the 4G boundary (IA-32) or 2^64
boundary (Intel EM64T mode), and write memory outside of the BTS/PEBS buffer.
Implication: Software that uses BTS/PEBS near the 4 G boundary (IA-32) or 2^64 boundary (Intel
EM64T mode), and defines the buffer such that it does not hold an integer multiple of
records can update memory outside the BTS/PEBS buffer.
Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS
buffer base is integer multiple of the corresponding record sizes as recommended in
the IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 3.
Status: For the steppings affected, see the Summary Table of Changes.
A40. Memory ordering failure may occur with snoop filtering third party
agents after issuing and completing a bus write invalidate line (BWIL)
or bus locked write (BLW) transaction
Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL
or BLW transaction, retain data from the addressed cache line in shared state even
though the specification requires complete invalidation. This data retention may also
occur when a BWIL transaction's self-snooping yields HITM snoop results.
Implication: A system may suffer memory ordering failures if its central agent incorporates
coherence sequencing which depends on full self-invalidation of the cache line
associated (1) with BWIL and BLW transactions, or (2) all HITM snoop results without
regard to the transaction type and snoop results source.
Workaround: 1. The central agent can issue a bus cycle that causes a cache line to be invalidated
(Bus Read Invalidate Line (BRIL) or BWIL transaction) in response to a processor-
generated BWIL (or BLW) transaction to insure complete invalidation of the associated
cache line. If there are no intervening processor-originated transactions to that cache
line, the central agent's invalidating snoop will get a clean snoop result.
Or
2. Snoop filtering central agents can:
a. Not use processor-originated BWIL or BLW transactions to update their snoop filter
information, or