Specification Update

Intel
®
Xeon
®
Processor 7000 Series 21
Specification Update, March 2010
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A6. Debug mechanisms may not function as expected
Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the
snoop phase it should be retried and the locked sequence restarted. However, if BINIT#
is also asserted during this transaction, the transaction will not be Certain debug
mechanisms may not function as expected on the processor. The cases are as follows:
• When the following conditions occur: 1) An FLD instruction signals a stack overflow
or underflow, 2) the FLD instruction splits a page-boundary or a 64 byte cache line
boundary, 3) the instruction matches a Debug Register on the high page or cache
line respectively, and 4) the FLD has a stack fault and a memory fault on a split
access, the processor will only signal the stack fault and the debug exception will
not be taken.
• When a data breakpoint is set on the ninth and/or tenth byte(s) of a floating point
store using the Extended Real data type, and an unmasked floating point exception
occurs on the store, the break point will not be captured.
• When any instruction has multiple debug register matches, and any one of those
debug registers is enabled in DR7, all of the matches should be reported in DR6
when the processor goes to the debug handler. This is not true during a REP
instruction. As an example, during execution of a REP MOVSW instruction the first
iteration a load matches DR0 and DR2 and sets DR6 as FFFF0FF5h. On a
subsequent iteration of the instruction, a load matches only DR0. The DR6 register
is expected to still contain FFFF0FF5h, but the processor will update DR6 to
FFFF0FF1h.
A data breakpoint that is set on a load to uncacheable memory may be ignored due to
an internal segment register access conflict. In this case the system will continue to
execute instructions, bypassing the intended breakpoint. Avoiding having instructions
that access segment descriptor registers e.g. LGDT, LIDT close to the UC load, and
avoiding serialized instructions before the UC load will reduce the occurrence of this
erratum.
Implication: Certain debug mechanisms do not function as expected on the processor.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A7. Cascading of performance counters does not work correctly when
forced overflow is enabled
Problem: The performance counters are organized into pairs. When the CASCADE bit of the
Counter Configuration Control Register (CCCR) is set, a counter that overflows will
continue to count in the other counter of the pair. The FORCE_OVF bit forces the
counters to overflow on every non-zero increment. When the FORCE_OVF bit is set, the
counter overflow bit will be set but the counter no longer cascades.
Implication: The performance counters do not cascade when the FORCE_OVF bit is set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
A8. EMON event counting of x87 loads may not work as expected
Problem: If a performance counter is set to count x87 loads and floating-point exceptions are
unmasked, the FPU operand (Data) pointer (FDP) may become corrupted.
Implication: When this erratum occurs, FPU operand (Data) pointer (FDP) may become corrupted.
Workaround: This erratum will not occur with floating point exceptions masked. If floating-point
exceptions are unmasked, then performance counting of x87 loads should be disabled.