Vol 1
Intel® Xeon® Product 2800/4800/8800 v2 Product Family 95
Datasheet Volume One, February 2014
Electrical Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. Referenced to the rising edge of TCK. Assuming minimum edge rate of 0.5 V/ns.
4. Referenced to the falling edge of TCK at the processor pad.
5. TRST_N is synchronized to TCK and asserted for 5 TCK periods while TMS is asserted.
6. Synchronous to PWRGOOD Input.
7. Referenced to the falling edge of TCK.
8. Referenced to the rising edge of TCK.
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Referenced to the rising edge of SVIDCLK at 0.5*V
TT.
3. T
High
is measured with respect to 0.7 * V
TT
. T
Low
time is measured with respect to 0.3 * V
TT
.
T5: TDO Clock to Output Valid Delay 5 ns 6-17 4
T5: BCLK0 to BPM_N [7:0] Output Valid Delay 1 8.6 ns 6-17
T5: BCLK0 to PRDY_N Output Valid Delay N/A 5 ns 6-17
T
s
: TDI, TMS Setup Time 6.5 ns 6-18 3
T
h
: TDI, TMS Hold Time 6.5 ns 6-18 3
T
s
: EAR_N Setup Time 1 uS 6-18
T
h
: EAR_N Hold Time 2 BCLK0 6-18 68
Boundary scan all non test output/float delay 0.5 25 ns 7
Boundary scan all non test input setup 15 ns 7,8
Boundary scan all non test input hold 15 ns 7,8
Table 6-27. Serial VID (SVID) Interface AC Timing Specifications
Symbol Parameter Min Typ Max Units Figure Notes
SVIDCLK Frequency 16.667 MHz 6-20 1
T
Period
Absolute Minimum SVIDCLK Period 59.3 62.5 62.6 ns 6-20 1
T
co
SVIDDATA Output Delay from SVIDCLK 5 ns 6-20 1,2
T
S
SVIDDATA Input Setup Time 1 ns 6-20 1
T
h
SVIDDATA Input Hold Time 5 ns 6-20 1,2
T
High/Low
SVIDCLK High and Low Time 30.0 31.5 33.0 ns 1,3
Table 6-28. Processor Asynchronous Sideband and Miscellaneous Signals AC
Specifications (Sheet 1 of 2)
Parameter Min Max Unit Figure Notes
1
T2: PROCHOT_N Input Pulse Width Low 500 uS 6-18
T1: PROCHOT_N Input Pulse Width High 5 uS 6-18
T2: PROCHOT_N Output Pulse Width Low 500 uS 6-18
T1: PROCHOT_N Output Pulse Width High 500 uS 6-18
T
s
: PROCHOT_N Setup Time 1 uS 6-19
T
h
: PROCHOT_N Hold Time uS 6-19
T7: FRB Cold Boot: RESET_N de-assertion to
PROCHOT_N de-assertion
1uS6-21
T8: FRB Warm Boot: PROCHOT_N assertion to
RESET_N assertion
1uS6-21
Table 6-26. JTAG and TAP Signal AC Specifications (Sheet 2 of 2)
T# Parameter Min Typ Max Unit Figure Notes
1,2
∞