Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 77
Datasheet Volume One, February 2014
Electrical Specifications
6.1.10 Reserved or Unused Signals
All Reserved (RSVD) signals must not be connected. Connection of these signals to
power, ground or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See Chapter 7, “Processor Land
Listing” for a land listing of the processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
SS
). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. Resistor values should be within ± 20% of the
impedance of the baseboard trace.
6.2 Signal Group Summary
Signals are grouped by buffer type and similar characteristics as listed in Table 6-5. The
buffer type indicates which signaling technology and specifications apply to the signals.
Table 6-4. Signal Description Buffer Types
Signal Description
Analog Analog reference or output. May be used as a threshold voltage or for buffer
compensation
Asynchronous
1
1. Qualifier for a buffer type.
Signal has no timing relationship with any system reference clock.
CMOS CMOS buffers: 1.05 V or 1.5 V tolerant
SMI2 Scalable Memory Interface Gen 2. These signals are the interface between the Intel®
Xeon® E7v2 and the scalable memory buffer. The pin names start with VMSE.
DMI2 Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express
2.0 and 1.0 Signaling Environment AC Specifications.
Intel® QPI Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect
signaling
Open Drain CMOS Open Drain CMOS (ODCMOS) buffers: 1.05V tolerant
PCI Express* PCI Express interface signals. These signals are compatible with PCI Express 3.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe specification.
Reference Voltage reference signal.
SSTL Source Series Terminated Logic (JEDEC SSTL_15)
Table 6-5. Signal Groups (Sheet 1 of 3)
Differential/Single
Ended
Buffer Type Signals
1
Intel SMI2 Reference Clocks
2
Differential SSTL Output VMSE{0/1/2/3}_CLK_D[N/P]
Intel SMI2 Command Signals
2
Single ended SSTL Output VMSE{0/1/2/3}_CMD[16:0]