Vol 1

PIROM
180 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
9.3.4.9 RES4: Reserved 4
This location is reserved. Writes to this register have no effect.
9.3.4.10 L2SIZE: L2 Cache Size
This location contains the size of the level-two cache in kilobytes. Writes to this register
have no effect. Data format is decimal.
Example: The Intel® Xeon® E7 v2 processor has a 256K L2 cache. Thus, offset
3Fh-40h will contain a value of 0100h.
9.3.4.11 L3SIZE: L3 Cache Size
This location contains the size of the level-three cache in kilobytes. Writes to this
register have no effect. Data format is decimal.
Example: The Intel® Xeon® E7 v2 processor has up to a 37.5 MB L3 cache. Thus,
offset 41h-42h will contain a value of 9600h.
9.3.4.12 VVMSE: VVMSE
This field contains the voltage requested for the VVMSE pins. This field is in mV and is
reflected in hex. Some systems read this offset to determine if all processors support
the same default VMSE settings. Writes to this register have no effect.
Example: A voltage of 1.350 VVMSE would contain an Offset 43-44h value of 1350h.
Offset: 39-4Ah
Bit Description
15:0 MIN VSA VID
0000h-FFFFh: mV
Offset: 3Bh-3Eh
Bit Description
31:0 RESERVED
00000000h-FFFFFFFFh: Reserved
Offset: 3Fh-40h
Bit Description
15:0 L2 Cache Size
0000h-FFFFh: KB
Offset: 41h-42h
Bit Description
15:0 L3 Cache Size
0000h-FFFFh: KB