Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 49
Specification Update January 2015
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF122 Surprise Down Error Status is Not Set Correctly on DMI Port
Problem: Due to this erratum, the Surprise_down_error_status (UNCERRSTS Device 0; Function
0; Offset 0x14C; bit 5) is not set to 1 when DMI port detects a surprise down error.
Implication: Surprise down errors will not be logged for the DMI port. This violates the PCIe* Base
Specification. Software that relies on this status bit may not behave as expected. It is
likely that conditions resulting in surprise down error would lead to other errors being
logged; a surprise down on DMI is not likely to be a silent event.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF123 Processor May Issue Unexpected NAK DLLP Upon PCIe* L1 Exit
Problem: Upon exiting the L1 link power state, the processor’s PCIe port may unexpectedly issue
a NAK DLLP (Data Link Layer Packet).
Implication: PCIe endpoints may unexpectedly receive and log a NAK DLLP.
Workaround: None identified
Status: For the affected steppings, see the “Summary Table of Changes”.
CF124 A MOV to CR3 When EPT is Enabled May Lead to an Unexpected Page
Fault or an Incorrect Page Translation
Problem: If EPT (extended page tables) is enabled, a MOV to CR3 may be followed by an
unexpected page fault or the use of an incorrect page translation.
Implication: Guest software may crash or experience unpredictable behavior as a result of this
erratum.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF125 Reading Intel® SMI2 Broadcast CSRs May Return Incorrect Data
Problem: Device 31, Functions 6,7 are Intel SMI2 (Scalable Memory Interface Gen 2) broadcast
CSRs; writing one0 broadcast CSR writes the corresponding CSR in each of the four
memory channels (Individual memory channel CSRs are located at Devices 17, 31;
Functions 0,1,4,5). Due to this erratum, reading SMI2 broadcast CSRs may return
incorrect data.
Implication: When this erratum occurs, software that reads broadcast CSRs may behave
unexpectedly.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF126 Intel QPI LLR.REQ Sent After a PHY Reset May Cause a UC Machine
Check in CRC16 Mode
Problem: When an Intel
®
QPI (Intel
®
QuickPath Interconnect) link is in CRC16 mode, the
LLR.REQ (Link Layer Retry Request) after a PHY Reset could trigger a UC
(uncorrectable) machine check with IA32_MC[4,5]_STATUS.MSCOD=0x12.
Implication: When this erratum occurs, a fatal machine check is generated, forcing a system reset.
Intel has not observed this erratum with any commercially available system.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.