Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 39
Specification Update January 2015
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF79 A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in
Certain Conditions
Problem: Under specific internal conditions, if software tries to write the IA32_FIXED_CTR1 MSR
(30AH) a value that has all bits [31:1] set while the counter was just about to overflow
when the write is attempted (i.e. its value was 0xFFFF FFFF FFFF), then due to this
erratum the new value in the MSR may be corrupted.
Implication: Due to this erratum, IA32_FIXED_CTR1 MSR may be written with a corrupted value.
Workaround: Software may avoid this erratum by writing zeros to the IA32_FIXED_CTR1 MSR,
before the desired write operation.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF80 #GP May be Signaled When Invalid VEX Prefix Precedes Conditional
Branch Instructions
Problem: When a 2-byte opcode of a conditional branch (opcodes 0F8xH, for any value of x)
instruction resides in 16-bit code-segment and is associated with invalid VEX prefix, it
may sometimes signal a #GP fault (illegal instruction length > 15-bytes) instead of a
#UD (illegal opcode) fault.
Implication: Due to this erratum, #GP fault instead of a #UD may be signaled on an
illegal instruction.
Workaround: None identified.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF81 Interrupt From Local APIC Timer May Not be Detectable While Being
Delivered
Problem: If the local-APIC timer’s CCR (current-count register) is 0, software should be able to
determine whether a previously generated timer interrupt is being delivered by first
reading the delivery-status bit in the LVT timer register and then reading the bit in the
IRR (interrupt-request register) corresponding to the vector in the LVT timer register. If
both values are read as 0, no timer interrupt should be in the process of being
delivered. Due to this erratum, a timer interrupt may be delivered even if the CCR is 0
and the LVT and IRR bits are read as 0. This can occur only if the DCR (Divide
Configuration Register) is greater than or equal to 4. The erratum does not occur if
software writes zero to the Initial Count Register before reading the LVT and IRR bits.
Implication: Software that relies on reads of the LVT and IRR bits to determine whether a timer
interrupt is being delivered may not operate properly.
Workaround: Software that uses the local-APIC timer must be prepared to handle the timer
interrupts, even those that would not be expected based on reading CCR and the LVT
and IRR bits; alternatively, software can avoid the problem by writing zero to the Initial
Count Register before reading the LVT and IRR bits.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF82 PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always
Operate with 32-bit Length Registers
Problem: In 64-bit mode, using REX.W=1 with PCMPESTRI and PCMPESTRM or VEX.W=1 with
VPCMPESTRI and VPCMPESTRM should support a 64-bit length operation with RAX/
RDX. Due to this erratum, the length registers are incorrectly interpreted as
32-bit values.
Implication: Due to this erratum, using REX.W=1 with PCMPESTRI and PCMPESTRM as well as
VEX.W=1 with VPCMPESTRI and VPCMPESTRM do not result in promotion to 64-bit
length registers.