Specification Update

Errata
Intel
®
Xeon
®
Processor E7 v2 Product Family 25
Specification Update January 2015
CF24 Long latency Transactions Can Cause I/O Devices On The Same Link to
Time Out.
Problem: Certain long latency transactions - for example, master aborts on inbound traffic,
locked transactions, peer-to-peer transactions, or vendor defined messages - conveyed
over the PCIe* and DMI2 interfaces can block the progress of subsequent transactions
for extended periods. In certain cases, these delays may lead to I/O device timeout
that can result in device error reports and/or device off-lining.
Implication: Due to this erratum, devices that generate PCIe* or DMI2 traffic characterized by long
latencies can interfere with other traffic types on the same link. This may result in
reduced I/O performance and device timeout errors. USB traffic can be particularly
sensitive to these delays.
Workaround: Avoid the contributing conditions. This can be accomplished by separating traffic types
to be conveyed on different links and/or reducing or eliminating long latency
transactions.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF25 Coherent Interface Write Cache May Report False Correctable ECC
Errors During Cold Reset.
Problem: The Integrated I/O's coherent interface write cache includes ECC logic to detect errors.
Due to this erratum, the write cache can report false ECC errors. This error is signaled
by asserting bit 1 (Write Cache Corrected ECC) in the IRPP0ERRST CSR (Bus 0; Device
5; Function 2; Offset 230H) or the IRPP1ERRST CSR (Bus 0; Device 5; Function 2;
Offset 2B0H).
Implication: If the coherent interface write cache ECC is enabled, the processor may incorrectly
indicate correctable ECC errors in the write cache.
Workaround: A BIOS workaround has been identified. Refer to Intel® Xeon® Processor E7 v2
Product Family-based platform CPU/Intel
®
QPI/Memory Reference Code version 1.0 or
later and release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF26 Combining ROL Transactions With Non-ROL Transactions or Marker
Skipping Operations May Result in a System Hang.
Problem: When Intel
®
QuickData Technology DMA ROL (Raid On Load) transactions and non-ROL
transactions are simultaneously active, and the non-ROL address offsets are not
cacheline boundary aligned, the non-ROL transaction's last partial cacheline data
write may be lost leading to a system hang. In addition, when Intel
®
QuickData
Technology DMA ROL transactions are active, marker skipping operations may lead to a
system hang.
Implication: When this erratum occurs, the processor may live lock resulting in a system hang.
Workaround: None identified. When ROL transactions and non-ROL transactions are simultaneously
active, all non-ROL address offsets must be aligned on cacheline boundaries. Further,
marker skipping operations may not be used on any DMA channel when ROL
transactions are active.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF27 Excessive DRAM RAPL Power Throttling May Lead to a System Hang or
USB Device Offlining.
Problem: DRAM RAPL (Running Average Power Limit) is a facility for limiting the maximum power
consumption of the memory subsystem. DRAM RAPL’s control mechanism constrains
the number of memory transactions during a particular time period. Due to this
erratum, a very low power limit can throttle certain memory subsystem configurations
to an extent that system failure, ranging from permanent loss of USB devices to system
hangs, may result.