Specification Update

Errata
20 Intel
®
Xeon
®
Processor E7 v2 Product Family
Specification Update January 2015
CF4 Intel
®
QuickData Technology DMA Lock Quiescent Flow Causes DMA
State Machine to Hang.
Problem: The lock quiescent flow is a means for an agent to gain sole ownership of another
agent's resources by preventing other devices from sending transactions. Due to this
erratum, during the lock quiescent flow, the Intel
®
QuickData Technology DMA read
and write queues are throttled simultaneously. This prevents subsequent read
completions from draining into the write queue, hanging the DMA lock state machine.
Implication: The DMA lock state machine may hang during a lock quiescent flow.
Workaround: Fix was provided in Reference Code version 1.0.000 or later.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF5 Suspending/Resetting a DMA XOR Channel May Cause an Incorrect
Data Transfer on Other Active Channels.
Problem: Suspending an active DMA XOR channel by setting CHANCMD.Suspend DMA bit
(Offset 84; Bit 2) while XOR type DMA channels are active may cause incorrect data
transfer on the other active legacy channels. This erratum may also occur while
resetting an active DMA XOR channel CHANCMD.Reset DMA bit (Offset 84; Bit 5).
CHANCMD is in the region described by CB_BAR (Bus 0; Device 4; function 0-7;
Offset 10H).
Implication: Due to this erratum, an incorrect data transfer may occur on the active legacy DMA
channels.
Workaround: Software must suspend all legacy DMA channels before suspending an active DMA XOR
channel (channel 0 or 1).
Status: For the affected steppings, see the “Summary Table of Changes”.
CF6 Quad Rank DIMMs May Not be Properly Refreshed During IBT_OFF
Mode.
Problem: The Integrated Memory Controller incorporates a power savings mode known as
IBT_OFF (Input Buffer Termination disabled). Due to this erratum, Quad Rank DIMMs
may not be properly refreshed during IBT_OFF mode.
Implication: Use of IBT_OFF mode with Quad Rank DIMMs may result in unpredictable system
behavior.
Workaround: A BIOS workaround has been identified. Refer to Intel® Xeon® Processor E7 v2
Product Family-based Platform CPU/Intel
®
QPI/Memory Reference Code version
1.0.006 or later and release notes.
Status: For the affected steppings, see the “Summary Table of Changes”.
CF7 Intel
®
QuickData Technology Continues to Issue Requests After
Detecting 64-bit Addressing Errors.
Problem: Intel
®
QuickData Technology uses the lower 48 address bits of a 64-bit address field.
Detection of accesses to source address, destination address, descriptor address, chain
address, or completion address outside of this 48-bit range are flagged as “64-bit
addressing errors” and should halt DMA processing. Due to this erratum, the Intel
®
QuickData Technology DMA continues to issue requests after detecting certain 64-bit
addressing errors involving RAID operations. The failing condition occurs for 64-bit
addressing errors in either a Channel Completion Upper Address Register
(CHANCMP_0, CHANCMP_1) (Bus 0; MMIO BAR CB_BAR [0:7]; Offset 98H, 9CH), or in
the source or destination addresses of a RAID descriptor.
Implication: Programming out of range DMA address values may result in unpredictable system
behavior.
Workaround: Ensure all RAID descriptors, CHANCMP_0, and CHANCMP_1 addresses are within the
48-bit range before starting the DMA engine.
Status: For the affected steppings, see the “Summary Table of Changes”.