Datasheet

8 Datasheet
7.2.12 KTSCR—KT Scratch ..............................................................................212
8 Host-Secondary PCI Express* Bridge Registers (D6:F0)
(Intel
®
3210 MCH only) .........................................................................................213
8.1 VID1—Vendor Identification ..............................................................................215
8.2 DID1—Device Identification...............................................................................216
8.3 PCICMD1—PCI Command .................................................................................216
8.4 PCISTS1—PCI Status........................................................................................218
8.5 RID1—Revision Identification ............................................................................219
8.6 CC1—Class Code .............................................................................................219
8.7 CL1—Cache Line Size .......................................................................................220
8.8 HDR1—Header Type.........................................................................................220
8.9 PBUSN1—Primary Bus Number..........................................................................220
8.10 SBUSN1—Secondary Bus Number......................................................................221
8.11 SUBUSN1—Subordinate Bus Number..................................................................221
8.12 IOBASE1—I/O Base Address .............................................................................222
8.13 IOLIMIT1—I/O Limit Address.............................................................................222
8.14 SSTS1—Secondary Status.................................................................................223
8.15 MBASE1—Memory Base Address........................................................................224
8.16 MLIMIT1—Memory Limit Address .......................................................................225
8.17 PMBASE1—Prefetchable Memory Base Address Upper...........................................226
8.18 PMLIMIT1—Prefetchable Memory Limit Address....................................................227
8.19 PMBASEU1—Prefetchable Memory Base Address Upper.........................................228
8.20 PMLIMITU1—Prefetchable Memory Limit Address Upper ........................................229
8.21 CAPPTR1—Capabilities Pointer ...........................................................................230
8.22 INTRLINE1—Interrupt Line................................................................................230
8.23 INTRPIN1—Interrupt Pin...................................................................................230
8.24 BCTRL1—Bridge Control ...................................................................................231
8.25 PM_CAPID1—Power Management Capabilities......................................................232
8.26 PM_CS1—Power Management Control/Status ......................................................233
8.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities ..........................................234
8.28 SS—Subsystem ID and Subsystem Vendor ID......................................................234
8.29 MSI_CAPID—Message Signaled Interrupts Capability ID........................................235
8.30 MC—Message Control.......................................................................................235
8.31 MA—Message Address......................................................................................236
8.32 MD—Message Data ..........................................................................................236
8.33 PE_CAPL—PCI Express* Capability List ...............................................................236
8.34 PE_CAP—PCI Express* Capabilities ....................................................................237
8.35 DCAP—Device Capabilities ................................................................................237
8.36 DCTL—Device Control.......................................................................................238
8.37 DSTS—Device Status .......................................................................................239
8.38 LCAP—Link Capabilities.....................................................................................240
8.39 LCTL—Link Control...........................................................................................242
8.40 LSTS—Link Status............................................................................................244
8.41 SLOTCAP—Slot Capabilities ...............................................................................245
8.42 SLOTCTL—Slot Control .....................................................................................246
8.43 SLOTSTS—Slot Status......................................................................................248
8.44 RCTL—Root Control..........................................................................................249
8.45 RSTS—Root Status ..........................................................................................250
8.46 PELC—PCI Express Legacy Control .....................................................................250
8.47 VCECH—Virtual Channel Enhanced Capability Header............................................251
8.48 PVCCAP1—Port VC Capability Register 1 .............................................................251
8.49 PVCCAP2—Port VC Capability Register 2 .............................................................252
8.50 PVCCTL—Port VC Control..................................................................................252
8.51 VC0RCAP—VC0 Resource Capability ...................................................................253