Datasheet

DRAM Controller Registers (D0:F0)

116 Datasheet

5.2.23 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG

B/D/F/Type: 0/0/0/MCHBAR

Address Offset: 650–651h

Default Value: 0000h

Access: RW, RO

Size: 16 bits

Channel 1 CYCTRK Precharge registers.

Bit Access

Default

Value

Description

15:11 RO 00000b Reserved

10:6 RW 00000b

Write To PRE Delayed (C1sd_cr_wr_pchg): This field indicates the minimum

allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the

same rank-bank. This field corresponds to t

in the DDR Specification.

5:2 RW 0000b

READ To PRE Delayed (C1sd_cr_rd_pchg): This field indicates the minimum

allowed spacing (in DRAM clocks) between the READ and PRE commands to the

same rank-bank

1:0 RW 00b

PRE To PRE Delayed (C1sd_cr_pchg_pchg): This field indicates the

minimum allowed spacing (in DRAM clocks) between two PRE commands to the

same rank.